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Electronics & Communication Engineering
NOC:VLSI Design Verification and test (Video)
Syllabus
Co-ordinated by :
IIT Guwahati
Available from :
2016-12-30
Lec :
1
Modules / Lectures
Introduction and Overview of VLSI Design
Introduction Part-1
Introduction Part-2
Overview of VLSI Design Flow
High Level Synthesis Overview Part 1
High Level Synthesis Overview Part 2
Scheduling in High-Level Synthesis
Scheduling in HLS (Part-1)
Scheduling in HLS (Part-2)
Scheduling in HLS (Part-3)
Scheduling in HLS (Part-4)
Scheduling in HLS (Part-5)
Scheduling in HLS (Part-6)
Scheduling in HLS (Part-7)
Resource Sharing and Binding in HLS
Resource Sharing and Binding in HLS (Part-1)
Resource Sharing and Binding in HLS (Part-2)
Resource Sharing and Binding in HLS (Part-3)
Resource Sharing and Binding in HLS (Part-4)
Resource Sharing and Binding in HLS (Part-5)
Resource Sharing and Binding in HLS (Part-6)
Resource Sharing and Binding in HLS (Part-7)
Logic Synthesis and Physical Design
Logic Synthesis (Part-1)
Logic Synthesis (Part-2)
Logic Synthesis (Part-3)
Physical Design (Part-1)
Physical Design (Part-2)
Physical Design (Part-3)
Introduction to Verification Techniques
Introduction to formal methods for design verification
Temporal Logic: Introduction and Basic Operations on Temporal Logic
Syntax and Semantics of CLT
Syntax and semantics of CTL, Equivalences between CTL formulas and Introduction to Model Checking
Syntax and semantics of CTL continued
Equivalences between CTL Formulas
Introduction to Model Checking
CTL Model checking Algorithms and Introduction to Binary Decision Diagrams
Model checking Algorithms
Model checking Algorithms continued.
Model Checking with Fairness
Binary Decision Diagram: Introduction and Construction
Binary Decision Diagram and Symbolic model checking
Ordered Binary Decision Diagram (OBDD)
Operation On OBDD
OBDD for State Transition Systems E
Symbolic Model Checking
Introduction to Digital Testing
Introduction to Digital VLSI Testing
Functional and Structural Testing
Fault Equivalence
Fault Simulation and Testability Measures
Fault Simulation I
Fault Simulation II
Fault Simulation III
Testability Measures (SCOAP)
Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
Combinational Circuit Test Pattern Generation
D-Algorithm I
D-Algorithm II
Sequential Circuit Testing and Scan Chains and Built In Self Test (BIST)
ATPG for Synchronous Sequential Circuits
Scan Chain based Sequential Circuit Testing I
Scan Chain based Sequential Circuit Testing II
BIST I
BIST II
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1
Introduction Part-1
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2
Introduction Part-2
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3
Overview of VLSI Design Flow
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4
High Level Synthesis Overview Part 1
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5
High Level Synthesis Overview Part 2
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6
Scheduling in HLS (Part-1)
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7
Scheduling in HLS (Part-2)
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8
Scheduling in HLS (Part-3)
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9
Scheduling in HLS (Part-4)
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Scheduling in HLS (Part-5)
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