| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction Part-1 | Download To be verified |
| 2 | Introduction Part-2 | Download To be verified |
| 3 | Overview of VLSI Design Flow | Download To be verified |
| 4 | High Level Synthesis Overview Part 1 | Download To be verified |
| 5 | High Level Synthesis Overview Part 2 | Download To be verified |
| 6 | Scheduling in HLS (Part-1) | Download To be verified |
| 7 | Scheduling in HLS (Part-2) | Download To be verified |
| 8 | Scheduling in HLS (Part-3) | Download To be verified |
| 9 | Scheduling in HLS (Part-4) | Download To be verified |
| 10 | Scheduling in HLS (Part-5) | Download To be verified |
| 11 | Scheduling in HLS (Part-6) | Download To be verified |
| 12 | Scheduling in HLS (Part-7) | Download To be verified |
| 13 | Resource Sharing and Binding in HLS (Part-1) | Download To be verified |
| 14 | Resource Sharing and Binding in HLS (Part-2) | Download To be verified |
| 15 | Resource Sharing and Binding in HLS (Part-3) | Download To be verified |
| 16 | Resource Sharing and Binding in HLS (Part-4) | Download To be verified |
| 17 | Resource Sharing and Binding in HLS (Part-5) | Download To be verified |
| 18 | Resource Sharing and Binding in HLS (Part-6) | Download To be verified |
| 19 | Resource Sharing and Binding in HLS (Part-7) | Download To be verified |
| 20 | Logic Synthesis (Part-1) | Download To be verified |
| 21 | Logic Synthesis (Part-2) | Download To be verified |
| 22 | Logic Synthesis (Part-3) | Download To be verified |
| 23 | Physical Design (Part-1) | Download To be verified |
| 24 | Physical Design (Part-2) | Download To be verified |
| 25 | Physical Design (Part-3) | Download To be verified |
| 26 | Introduction to formal methods for design verification | Download To be verified |
| 27 | Temporal Logic: Introduction and Basic Operations on Temporal Logic | Download To be verified |
| 28 | Syntax and Semantics of CLT | Download To be verified |
| 29 | Syntax and semantics of CTL continued | Download To be verified |
| 30 | Equivalences between CTL Formulas | Download To be verified |
| 31 | Introduction to Model Checking | Download To be verified |
| 32 | Model checking Algorithms | Download To be verified |
| 33 | Model checking Algorithms continued. | Download To be verified |
| 34 | Model Checking with Fairness | Download To be verified |
| 35 | Binary Decision Diagram: Introduction and Construction | Download To be verified |
| 36 | Ordered Binary Decision Diagram (OBDD) | Download To be verified |
| 37 | Operation On OBDD | Download To be verified |
| 38 | OBDD for State Transition Systems E | Download To be verified |
| 39 | Symbolic Model Checking | Download To be verified |
| 40 | Introduction to Digital VLSI Testing | Download To be verified |
| 41 | Functional and Structural Testing | Download To be verified |
| 42 | Fault Equivalence | Download To be verified |
| 43 | Fault Simulation I | Download To be verified |
| 44 | Fault Simulation II | Download To be verified |
| 45 | Fault Simulation III | Download To be verified |
| 46 | Testability Measures (SCOAP) | Download To be verified |
| 47 | Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras | Download To be verified |
| 48 | D-Algorithm I | Download To be verified |
| 49 | D-Algorithm II | Download To be verified |
| 50 | ATPG for Synchronous Sequential Circuits | Download To be verified |
| 51 | Scan Chain based Sequential Circuit Testing I | Download To be verified |
| 52 | Scan Chain based Sequential Circuit Testing II | Download To be verified |
| 53 | BIST I | Download To be verified |
| 54 | BIST II | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |