It may be noted that each net of the circuit has a 4 word array, where the

• first bit corresponds to normal condition of the circuit,
• the second for s-a-0 fault at I2(G1),
• the third bit for s-a-1 fault at OG2,
• the fourth for s-a-0 at I2.

The first bit of the array at I1 is 1, implying that under normal condition I1=1 (i.e., input I1 is 1 by the random pattern). Similarly, input I2 is 1 by the random pattern. The second bit of the array for I1 is 1 because under the s-a-0 fault at I2(G1), I1 has value of 1; similarly the third and fourth bits of the array for I1 are 1. In a similar way, the second and third bits of the array at I2 are 1. However, the fourth bit of the array at I2 is 0, because under the s-a-0 fault at I2, net I2 has value of 0.

The array at I2(G1) is a replica of the array at I2, but after changing the second bit to 0 as under s-a-0 fault at I2(G1), net I2(G1) has the value 0. The array at I2(G2) is a replica of the array at I2 as no fault is considered at I2(G2).

So, to fill the values of the array in a fanout branch when the values at the stem are known, there are two steps

1. Copy the values of array of the stem to the arrays of the branches
2. If there is any s-a-0 (or s-a-1) fault is a branch, change the corresponding bit of the array to 0 (or 1).

The array at OG1 is obtained by parallel logic AND operation on the words at the input lines I1 and I2(G1). The array at OG2 is obtained by parallel logic NOT operation on the word at the input line I2(G2) and making the third bit as 1 (as it corresponds to s-a-1 fault at OG2). So, to fill the values of the array in the output of a gate when the values at the input are known, there are two steps

1. Obtain the values of array by parallel logic operation on the bits of the input words.
2. If there is s-a-0 (or s-a-1) fault at the output of the gate, change the corresponding bit of the array to 0 (or 1).

In a similar way the whole example can be explained.The array at O1 is 0010. It implies that on the input I1=1 and I2=1

•  O1 is 0 under normal condition

•  O1 is 0 under s-a-0 fault at I2(G1),

•  O1 is 1 under s-a-1 fault at OG2,

•  O1 is 0 under s-a-0 at I2.

It can be seen that only s-a-1 fault at OG2 causes a measurable difference at primary output O1 under normal and faulty condition for input pattern I1=1,I2=1. So pattern I1=1,I2=1 can detect only s-a-1 fault at OG2 (at output O1) but cannot detect s-a-0 fault at I2(G1) and s-a-0 fault at I2.

The array at O2 is 1010. It implies that on the input I1=1 and I2=1

•  O2 is 1 under normal condition

•  O2 is 0 under s-a-0 fault at I2(G1),

•  O2 is 1 under s-a-1 fault at OG2,

•  O2 is 0 under s-a-0 fault at I2.

It can be seen that s-a-0 fault at I2(G1) and s-a-0 fault at I2 cause a measurable difference at primary output O2 under normal and faulty condition for input pattern I1=1,I2=1. So pattern I1=1,I2=1 at output O2 can detect s-a-0 fault at I2(G1) and s-a-0 fault at I2 but cannot detect s-a-1 fault at OG2. However, I1=1,I2=1 at output O1 detects s-a-1 fault at OG2. So all the three faults are detected by I1=1,I2=1.

Thus, under once scan of the circuit, information about three faults for a random pattern is discovered. It may be noted from Figure 7, that three scans of the circuit were required to find the same fact. So parallel fault simulation, speeds us the serial fault simulation scheme by w-1 times.

After an iteration of parallel fault simulation, >> set of w-1 faults are considered and the procedure repeated. After all the faults are considered (i.e., total number of faults/(w-1) iterations) the ones detected by the random pattern are dropped. >> another random pattern is taken and a new set of iterations are started.

So parallel fault simulation speeds up serial fault simulation w-1 times, but for a random pattern more than one iterations are required. In the >> section we will see a scheme where in one iteration, information about ALL faults for a random pattern can be generated.