Figure 5. Testing using set/reset flip-flops and shift register
Figure 6. Input output block diagram of the circuit under test (Figure 5) with shift register
The following are the pros and cons of shift register based testing and ATPG.
Pros:
• ATPG algorithm does not require time frame expansion approach and flip-flops can be directly controlled from the register. So ATPG complexity is lower than time frame expansion approach.
• I/O requirements for testing is minimal (only 3)
Cons:
• Area overhead of the shift register is high (twice the number of flip-flops in the circuit)
• Test pattern application time is almost same as in the time frame expansion approach. Applying bit sequence in the shift register (required for setting/resetting the flip-flops) takes 2 X nffs pulses of the clock of the register.
In the next section we will discuss another scheme similar to shift resister based testing called “scan chain”. In scan chain based technique the flip-flops are directly controllable and I/O requirements are minimal. However, on the other side there is no requirement of the additional shift register and separate set/reset lines in flip-flops; due to these two points scan chain based scheme is widely accepted in VLSI testing.