Now let us consider another circuit shown in Figure 7 with fanouts, and see the stuck-at fault locations especially in the fanout net.

Figure 7: Stuck-at fault locations in a circuit with fanouts

Output of gate G1 drives inputs of gate G2 and G3. Here, the output net of G1 has three fault locations for stuck-at faults rather than one, as marked in Figure 7 by black circles. One point corresponds to output of gate G1 (OG1) and the other two to the inputs of gate G2 (OG1') and G3 (OG1”). In other words, a net having fanout to k gates will have k+1 stuck at fault locations; one for the gate output (stem of the fanout) and the others for the inputs of the gates that are driven (branches of the fanout). When the stuck-at fault is at the output of the gate (OG1, in this case) then all the nets in the fanout have the value corresponding to the fault. However, if fault is in one fanout (OG1' or OG1”, in this case) then only the corresponding gate being driven by the branch of the fanout is effected by the stuck-at fault and others branches are not effected.

Now the question remains, “if fanout along with all its branches is a single electrical net, then why fault in a branch does not affect the others”. The answer is again by history of testing of chips with single-stuck at fault model. It may be noted that a net getting physically stuck may not occur. When we perform structural testing with single stuck-at fault model, we verify that none of the sites have any stuck-at fault. Assuring this ensures with 99.9% accuracy that the circuit has no defect. Considering different branches of a fanout independent, more locations for stuck-at faults are created. Testing history on stuck-at faults has shown that this increased number of locations is required to ensure the 99.9% accuracy.

To summarie, single stuck-at fault model is characterized by three assumptions:

1. Only one net is faulty at a time.

2. The faulty net is permanently set to either 0 or 1.

3. The branches of a fanout net are independent with respect to locations and affect of a stuck-at fault.

In general, several stuck-at faults can be simultaneously present in the circuit. A circuit with n lines can have 3ⁿ -1 possible stuck line combinations; each net can be: s-a-1, s-a-0, or fault-free. All combinations except one having all nets as normal are counted as faults. So handling multiple stuck-at faults in a typical circuit with some hundreds of thousands of nets is infeasible. As single stuck-at fault model is manageable in number and also provides acceptable quality of test solution, it is the most accepted fault model.

Now we illustrate structural testing with single stuck-at fault model.