4. Structural Testing with Fault Models

Structural testing with fault models involves verifying each unit (gate and flip flop) is free from faults of the fault model.

 4.1 What is Fault Models

A model is an abstract representation of a system. The abstraction is such that modeling reduces the complexity in representation but captures all the properties of the original system required for the application in question.

So, fault model is an abstraction of the real defects in the silicon such that

........•  the faults of the model are easy to represent

........•  should ensure that if one verifies that no faults of the model are in the circuit, quality of test solution is maintained.

In perspective of the present discussion, the following definitions are important

Defect: A defect in a circuit is the unintended difference between the implemented hardware in silicon and its intended design.

Error: An error is an “effect” of some “defect.”

Fault: Abstraction of a “defect” at the fault modeling level is called a fault.

Let us consider an AND G1 of Figure 2, where due to incomplete doping of metal, net I1 is left unconnected with the gate; this is illustrated in Figure 5. This unconnected net I1 is the defect. Error is, when I1=1, I2=1,I3=1,I4=1, I5=1 but OG1=0 (should be 1 in normal case). Fault is, net I1 is stuck at 0 (when gate is modeled at binary logic level).

Figure 5: AND gate with one net open