1. Introduction

 In the last lecture we learnt that Digital VLSI testing is to verify if logic functionality is as per the specifications. For example, for the 2 input NAND gate the test would comprise only the 4 input combinations and verifying the output. The time required to verify anything more than logic functionally is beyond practical limits in terms of ATE time, man hours, cost of the chip etc. Also, the quality of test solution (i.e., proper binning of normal and faulty chips) is acceptable for almost all classes of circuits. This is called Functional Testing.

Now let us consider a digital circuit with 25 inputs which does bit wise ANDing of the inputs. The black box of the circuit is shown in Figure 1. The complete functional test is given in Table 1.

Figure 1. Circuit for Bit wise ANDing
Table 1. Test patterns for functional testing of circuit in Figure 1

Test Pattern No.	Test Pattern	Output
1	0000000000000000000000000	0
2	0000000000000000000000001	0
..................	……………………………………………..	0
225	1111111111111111111111111	1

We need to apply 2²⁵ test patterns to complete the test. If we apply 1000000 patterns per second (Mega Hz Tester), then time required is 33 Seconds per chip. In a typical scenario about 1 million chips are to be tested in a run, thereby taking about 33000000 Seconds or 550000 Hours or 22916 Days or 62 years. So one can understand the complexity when a circuit has 100+ inputs. So for a typical circuit even Functional Testing cannot be performed due to extremely high testing time.

To solve this issue we perform Structural Testing, which takes many fold less time compared Functional Testing yet maintaining the quality of test solution. Structural testing, introduced by Eldred, verifies the correctness of the specific structure of the circuit in terms of gates and interconnects. In other words, structural testing does not check the functionality of the entire circuit rather verifies if all the structural units (gates) are fault free. So structural testing is a kind of functional testing at unit (gate) level.In the next section we elaborate the gain in test time for structural testing using the example of the 25 input ANDing circuit. Also, the cost that needs to be paid is illustrated using the same example.

2. Structural Testing: An Example Of 25 Input Bit Wise ANDing Circuit

To perform structural testing a white box view of the circuit (i.e., gate level implementation) is required. Following that functional testing would be performed on the individual gates. Figure 2 shows a gate level implementation of the 25 input bit wise ANDing circuit (of Figure 1).
Structural testing for the circuit would comprise the patters discussed below:

1. Testing of the 5 input AND gate G1 with the input patterns as given in Table 2.

Table 2. Test patterns for testing of gate G1

	Test Pattern (I1,I2,I3,I4,I5)	Output
1	00000	0
2	00001	0
…………	……………………………………………..	0
32	11111	1