Step 3: Logic Synthesis

After the RTL is verified to be equivalent to system specification, logic synthesis is performed by CAD tools. In logic synthesis all blocks of the RTL circuit is transformed into logic gates and flip-flops. For the running example all the blocks namely, adder, multiplexers, control logic etc. need to be synthesized to logic gates. Here, we will illustrate synthesis only for the adder module and for the rest, similar procedure holds. We will discuss a typical procedure here in brief and details will be explained in the “DESIGN” module of the course.

We first determine the Boolean function of the adder module, in terms of mean terms. Table 1 illustrates the input –output of the adder module.

Table 1. Input –output of the adder module

a	b	Out1(sum)	Out1(carry)
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

From the table we have Boolean equations for

Out1(sum)= and Out1(carry)=ab

After the equations are obtained they need to be minimized so that the circuit can be implemented using minimal number of gates. Karnaugh map, Quine–McCluskey algorithm etc. [6] are some standard techniques to minimize Boolean functions. In this example of the adder, the equations are already minimized and can be directly converted to Boolean gate implementation as shown in Figure 8. Karnaugh map and Quine–McCluskey techniques work well if the number of inputs is less. However, in case of practical VLSI circuits the number of inputs are in orders of hundreds, so minimization is carried out using heuristics techniques, which will be discussed in the “DESIGN” module of the course.

Again equivalence of logic synthesis output should be established with RTL design.

Figure 8. Circuit after logic synthesis for the adder block (of Figure 5)

Step 4: Backend

Once the logic level output of the circuit is obtained we move to backend phase of the design process. Broadly speaking, in backend we start with a software version of the silicon die where the chip will be finally fabricated. In the process, we first make a broad plan regarding placement of gates, flip-flops etc. (output of logic synthesis) in appropriate places in the software representation of the chip; this process is called Floorplan. Following that, we decide on the exact locations in the die (software representation) where the circuit components are placed; this is called Placement. Once placement is done, we make the required interconnections (as given in the logic circuit) among the gates that are placed in exact positions in the die; this process is called Routing. The main aim of Floorplan, Placement and Routing is to minimize silicon area, minimize signal delays, well distributed power flow etc., subject to accommodating all the components of the chip and adhere to the design check rules [7].

In this course we will not discuss the Backend phase of design flow; for details the reader is refereed to [7].

Again equivalence of output of Backend process should be established with logic design. In this process we extract the logic circuit from the placed and routed circuit in the die (software representation) and equivalence is verified against logic design (output of logic synthesis).