2.  Flow of VLSI “DESIGN-VERIFICATION-TEST” using an example

 

Figure 1. VLSI Design, Verification and Test Flow

Figure 1 illustrates a typical VLSI DESIGN-VERIFICATION-TEST flow.

Step1: Specification Design

In a typical VLSI flow, we start with system specifications, which is nothing but technical representation of design intent. To explain the flow, the following example will be used through this section.

Example:

Specification: out1=a+b; out2=c+d; where a,b,c,d are single bit inputs and out1,out2 are two bit outputs (sum and carry).

Step 2: High level Synthesis

High-Level Synthesis (HLS) algorithms are used to convert specifications into Register Transfer Level (RTL) circuits.

HLS, sometimes referred to as architectural synthesis is an automated design procedure that interprets an algorithmic description of the design intent and creates hardware at RTL that implements that behavior [3]. The input to a HLS tool is design intent written in some high level hardware definition language like SystemC, System Verilog etc. The HLS tool first schedules the computations (required to meet the specifications) at different control steps. The computations scheduled at each control step contains operations which can be performed in a single clock cycle in the hardware. Following that, depending on availability of hardware units and time constraints, the scheduled computations (comprising instructions and variables) are allocated and binded to the hardware units like adders, multipliers, multiplexors, registers, wires etc.

Example:

In the example there are two operations (addition of single bit numbers) and none of them depend on each other. So both the operations can be scheduled in a single control step. However, if there are dependencies e.g., out1=a+b; out2=out1+d; then “out1=a+b;” is scheduled in 1 st control step whereas “out2=out1+d;” is scheduled in 2 nd control step. Figure 2 illustrates scheduling of the operations of the example.