1. Introduction VLSI Design

The functionality of electronics equipments and gadgets has achieved a phenomenal growth over the last two decades while their physical sizes and weights have come down drastically. The major reason is due to the rapid advances in integration technologies, which enables fabrication of millions of transistors in a single Integrated Circuit (IC) or chip. IC (used interchangeably with “chip” in this lecture) is a device having multiple transistors with interconnects manufactured on a single silicon substrate. Integration with a complexity of 10's of transistors is called Small Scale Integration, with 100's is Medium Scale Integration (MSI), with 1000's is Large Scale Integration (LSI), with 10,000 it is Very Large Scale Integration (VLSI) [1]. As a very huge number of components can be integrated in a single IC fabricated using VLSI technology, the variant of functionalities provided by such ICs can be as large as those which were provided by thousands of LSI ICs. In other words, systems can be implemented in a VLSI IC. However, with this rise in functionality of VLSI ICs, design problem has become more challenging and complex. To address this complexly issue, post design steps are automated using Computer Aided Design (CAD) tools. However, even designs using automated CAD tools may have bugs. Also, due to extremely large size of the design space it is not possible to verify correctness of the design under all possible situations. So techniques are required that can verify, without exercising exhaustive input-output combinations, that the design meets all the input specifications; this technique is called formal verification. Finally, when the design meets all specifications (as it is formally verified) it is manufactured and sent to market. In VLSI designs as millions of transistors are packed into a single chip, the device and interconnect sizes are extremely small and so are the inter-component distances. This may lead to manufacturing defects and all the chips need to be physically tested by giving input signals from a pattern generator and comparing responses using a logic analyzer; this process is called testing. So, in the process of manufacturing a VLSI IC there are three broad steps: DESIGN-VERIFICATION-TEST. There are algorithms and CAD tools which automate these three steps.

VLSI ICs can be divided into analog, digital or mixed-signal (both analog and digital on the same chip) based on their functionality. Digital ICs can contain logic gates, flip-flops, multiplexers, and other circuits which work using binary mathematics to process "one" and "zero" signals. Analog ICs, such as current mirrors, voltage followers, filters, OPAMPs etc. work by processing continuous signals. They perform functions like amplification, active filtering, demodulation etc. When single IC has both analog and digital components it is called mixed signal IC e.g, Analog to Digital Converter (ADC). The automation algorithms and CAD tools are mainly available for digital ICs because digital circuits comprise millions of components and transformation of design specifications to silicon implementation can be accomplished using logical procedures (which can be converted to algorithms and tools) [2]. However, most of the analog circuits comprise less than hundred devices and its design is like an “art” which is best performed by designers with “aid” of some CAD tools (which provides feedback to designer if the manual design is progressing fine etc.) [2]. In this course we will deal only with digital VLSI circuits. Henceforth, in this course VLSI IC would imply digital VLSI ICs only and whenever we want to discuss about analog or mixed signal ICs it will be mentioned explicitly. Also, in this course the terms ICs and chips would mean VLSI ICs and chips.

This course is concerned with algorithms required to automate the three steps “DESIGN-VERIFICATION-TEST” for Digital VLSI ICs. Although there are individual courses catering to each step, in this course we will try to give a complete picture of algorithms required to automate the entire flow “DESIGN-VERIFICATION-TEST”. This course will give you a comprehensive idea of algorithms required in CAD tools for the whole digital VLSI flow, however, to cover the entire flow at certain points we will go to a limited depth and provide references to the details.

In the first lecture, we will introduce the entire flow of “DESIGN-VERIFICATION-TEST” using a simple example. Also, we will not go into the algorithms required to automate the steps, rather we will point the requirements of the algorithms.