Design
Module I: Introduction
       Lecture I: Introduction to Digital VLSI Design Flow
       Lecture II:  High Level Design Representation
       Lecture III: Transformations for High Level Synthesis

Module II: Scheduling, Allocation and Binding
       Lecture I:   Introduction to HLS: Scheduling, Allocation and Binding Problem
       Lecture II and III:  Scheduling Algorithms           
       Lecture IV: Binding and Allocation Algorithms

Module III: Logic Optimization and Synthesis
       Lecture I,II and III:  Two level Boolean Logic Synthesis
       Lecture IV: Heuristic Minimization of Two-Level Circuits
       Lecture V: Finite State Machine Synthesis
       Lecture VI: Multilevel Implementation

Verification
Module IV: Binary Decision Diagram
       Lecture-I: Binary Decision Diagram: Introduction and construction
       Lecture-II: Ordered Binary Decision Diagram
       Lecture-III: Operations on Ordered Binary Decision Diagram
       Lecture-IV: Ordered Binary Decision Diagram for Sequential Circuits

Module V: Temporal Logic
       Lecture-I: Introduction and Basic Operations on Temporal Logic
       Lecture-II: Syntax and Semantics of CTL
       Lecture-III: Equivalence between CTL Formulas

Module VI: Model Checking
       Lecture-I: Verification Techniques
       Lecture-II, III and IV: Model Checking Algorithm
       Lecture-V: Symbolic Model Checking

Test
Module  VII: Introduction to Digital Testing
       Lecture-I: Introduction to Digital VLSI Testing
       Lecture-II:  Functional and Structural Testing
       Lecture-III: Fault Equivalence

Module  VIII: Fault Simulation and Testability Measures
       Lecture-I, II and III: Fault Simulation
       Lecture-IV: Testability Measures (SCOAP)

Module IX: Combinational Circuit Test Pattern Generation
       Lecture-I: Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
       Lecture-II and III: D-Algorithm

Module  X: Sequential Circuit Testing and Scan Chains
       Lecture-I:  ATPG for Synchronous Sequential Circuits
       Lecture-II and III: Scan Chain based Sequential Circuit Testing

Module XI: Built in Self test (BIST)
       Lecture I and II: Built in Self Test
       Lecture III and IV:  Memory Testing