| Module Name | Download |
|---|---|
| noc19_cs04_Assignment1 | noc19_cs04_Assignment1 |
| noc19_cs04_Assignment10 | noc19_cs04_Assignment10 |
| noc19_cs04_Assignment11 | noc19_cs04_Assignment11 |
| noc19_cs04_Assignment12 | noc19_cs04_Assignment12 |
| noc19_cs04_Assignment13 | noc19_cs04_Assignment13 |
| noc19_cs04_Assignment2 | noc19_cs04_Assignment2 |
| noc19_cs04_Assignment3 | noc19_cs04_Assignment3 |
| noc19_cs04_Assignment4 | noc19_cs04_Assignment4 |
| noc19_cs04_Assignment5 | noc19_cs04_Assignment5 |
| noc19_cs04_Assignment6 | noc19_cs04_Assignment6 |
| noc19_cs04_Assignment7 | noc19_cs04_Assignment7 |
| noc19_cs04_Assignment8 | noc19_cs04_Assignment8 |
| noc19_cs04_Assignment9 | noc19_cs04_Assignment9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Model of Computer and Working Principle | Download |
| 2 | Digital Logic Building Blocks | Download |
| 3 | Information Representation and Number Systems | Download |
| 4 | Basic Elements of a Processor | Download |
| 5 | Storage and I/O Interface | Download |
| 6 | Execution of Program and Programming Languages | Download |
| 7 | Components of Central Processing Unit (CPU) and External Interface | Download |
| 8 | Main Memory | Download |
| 9 | Instruction Execution | Download |
| 10 | Instruction Format | Download |
| 11 | Instruction Set | Download |
| 12 | Addressing Modes | Download |
| 13 | Flags and Conditional Instructions | Download |
| 14 | Instruction: Procedure CALL/RETURN | Download |
| 15 | Instruction Cycle and Micro-operations | Download |
| 16 | Control Signals and Timing Sequence | Download |
| 17 | Control Signals for Complete Instruction Execution | Download |
| 18 | Handling Different Addressing Modes | Download |
| 19 | Handling Control Transfer Instructions | Download |
| 20 | Design of Hardwired controlled Control Unit | Download |
| 21 | Microinstructions and Microprograms | Download |
| 22 | Organization and Optimization of Microprogrammed controlled Control Unit | Download |
| 23 | Different Internal CPU Bus Organization | Download |
| 24 | Basics of Memory and Cache | Download |
| 25 | Basics of Memory and Cache (Part-2) | Download |
| 26 | Direct-mapped Caches: Misses, Writes and Performance | Download |
| 27 | Associative and Multi-level Caches | Download |
| 28 | Summary | Download |
| 29 | Basics of Virtual Memory and Address Translation | Download |
| 30 | Paging and Segmentation | Download |
| 31 | TLBs and Page Fault Handling | Download |
| 32 | Cache Indexing and Tagging Variations, Demand Paging | Download |
| 33 | Page Replacement Algorithms | Download |
| 34 | Page Frame Allocation and Thrashing | Download |
| 35 | Summary of Memory Sub-system Organization | Download |
| 36 | Input-Output Primitives | Download |
| 37 | Interrupt Driven I/O | Download |
| 38 | DMA Transfer | Download |
| 39 | Storage Devices | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Model of Computer and Working Principle | Download Verified |
| 2 | Digital Logic Building Blocks | Download Verified |
| 3 | Information Representation and Number Systems | Download Verified |
| 4 | Basic Elements of a Processor | Download Verified |
| 5 | Storage and I/O Interface | Download Verified |
| 6 | Execution of Program and Programming Languages | Download Verified |
| 7 | Components of Central Processing Unit (CPU) and External Interface | Download Verified |
| 8 | Main Memory | Download Verified |
| 9 | Instruction Execution | Download Verified |
| 10 | Instruction Format | Download Verified |
| 11 | Instruction Set | Download Verified |
| 12 | Addressing Modes | Download Verified |
| 13 | Flags and Conditional Instructions | Download Verified |
| 14 | Instruction: Procedure CALL/RETURN | Download Verified |
| 15 | Instruction Cycle and Micro-operations | Download Verified |
| 16 | Control Signals and Timing Sequence | Download Verified |
| 17 | Control Signals for Complete Instruction Execution | Download Verified |
| 18 | Handling Different Addressing Modes | Download Verified |
| 19 | Handling Control Transfer Instructions | Download Verified |
| 20 | Design of Hardwired controlled Control Unit | Download Verified |
| 21 | Microinstructions and Microprograms | Download Verified |
| 22 | Organization and Optimization of Microprogrammed controlled Control Unit | Download Verified |
| 23 | Different Internal CPU Bus Organization | Download Verified |
| 24 | Basics of Memory and Cache | Download Verified |
| 25 | Basics of Memory and Cache (Part-2) | Download Verified |
| 26 | Direct-mapped Caches: Misses, Writes and Performance | Download Verified |
| 27 | Associative and Multi-level Caches | Download Verified |
| 28 | Summary | Download Verified |
| 29 | Basics of Virtual Memory and Address Translation | Download Verified |
| 30 | Paging and Segmentation | Download Verified |
| 31 | TLBs and Page Fault Handling | Download Verified |
| 32 | Cache Indexing and Tagging Variations, Demand Paging | Download Verified |
| 33 | Page Replacement Algorithms | Download Verified |
| 34 | Page Frame Allocation and Thrashing | Download Verified |
| 35 | Summary of Memory Sub-system Organization | Download Verified |
| 36 | Input-Output Primitives | Download Verified |
| 37 | Interrupt Driven I/O | Download Verified |
| 38 | DMA Transfer | Download Verified |
| 39 | Storage Devices | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Download |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |