Now,  is propagated through gate-5, which is in D-frontier. Now as gate-5 is driving a primary output, the fault effect is propagated successfully. This results in e=1, by backward implication. This finishes a successful generation of a test pattern by D-algorithm, as there is no inconsistency and fault effect (, here) reaches a primary output.  Test pattern is a=0,b=1,c=1,d=1,e=1. This step is illustrated in Figure 7(n).

Figure 7(n): Backward implication for e =1 and successful test pattern generation

3. Why advanced ATPG algorithms: PODEM [2] and FAN[3]

In this course, we will not go into the details of the advanced ATPG algorithms. Interested readers can go through the references mentioned above. However, we will point out the drawbacks in the D-algorithm and briefly discuss how they were handled in the advanced ATPG algorithms.
If we observe the steps in the D-algorithm we can notice that it has three basic points

• Sensitize the fault location  (i.e., D/ in the fault net)
• Propagation of D/ to a primary output, using any gates in D-frontier
• Use any values of signals as per forward and backward implications, to get the values of primary inputs, which sensitize the fault and propagate it to an output.

At any point, backtrack is required in case D-frontier is exhausted or an inconsistency is found.
So it may be stated that D-algorithm provides all the steps required for ATPG, however, says nothing about which of the alternatives are to be taken for propagation of D/ or values of signals as per forward and backward implications. In other words, the algorithm does not prioritize among the options available in case of propagation of D/ or signal assignment during implications. Also, in case of backtrack, information regarding the reason for inconsistency is not used for future selection of alternatives.
So the advanced algorithms basically improve D-algorithm by providing a guided choice of alternatives based on several testability measures namely,

• After a fault is sensitized, if there are more than one gate in the D-frontier, then choice can be made based on conditions like,

• The shortest path (in terms of number of gates) from the fault site to a primary output is to be taken
• The path having gate inputs (other than the one used for fault propagation) with low values of CC1 and CC0 (SCOAP values) are preferred than the ones with higher values.
• If more than one signal values are possible for nets after implication, consider the one that will result in low CC1 and CC0 values.
• Use the reasons for inconsistency for future selection of alternatives

5. Conclusion

Till this point in the course you might be surprised because we have talked only about testing of combinational circuits. However, most of the practical circuits are sequential ones.  In the next module we will introduce ATPG for sequential circuits. Following that we will discuss a design for testability (DFT) technique called scan chain which converts sequential circuits to virtual combinational ones. So all the techniques discussed for combinational circuits will hold for sequential ones with DFT.