5.  Binding using Iterative Refinement

Binding using iterative refinement, as the name suggests, starts with an arbitrary “feasible” binding and at each step of iteration, variables (or operations) are swapped in between the registers (or operations) such that the new binding remains feasible. If the new binding comprises less interconnect area than the previous one, the new binding replaces the old one. Iteration continues until the interconnect area reaches the desired level or new iterations are not able to improve the area.

For example, we may start with the binding given in Figure 9. Then we may swap variable out2 and “NULL” between R2 and R3; this schedule is better than the old one as it requires two multiplexers (Figure 2) while the old one requires three multiplexers (Figure 10). Similarly, we carry on with the iterations by swapping variables until we get the desired interconnect area or we find that there has been no improvement since last few (which can be a user defined threshold) iterations.

The scheme discussed above is the basic skeleton of iterative refinement based binding and there are several disadvantages. Just pair wise exchange of variables may not explore the full design space. Further, iterative schemes may be stuck at local minima [3]. In other words, even if some iteration (binding configuration C1 to C2, say) leads to increase in interconnect area, C2 may be still taken, because subsequent swapping iterations from C2 lead to an optimal area, which cannot be achieved from C1. Several evolutionary algorithms like simulated annealing, partial swam optimization etc. are applied to solve the iterative binding problem; the details can be found in [3,4].

6.  Conclusions

In this lecture, we discussed three algorithms to solve the binding sub-step of HLS problem namely, clique partitioning, left edge algorithm and iterative refinement. Once the three sub-steps of HLS are completed, Register Transfer Level circuit is generated. In the next module we will discuss algorithms to convert Register Transfer Level circuits to gate level designs which can be Placed/Routed and finally fabricated.