1.Introduction: Why is memory testing different?

Till now we have been looking into VLSI testing, only from the context where the circuit is composed of logic gates and flip-flops. However, memory blocks form a very important part of digital circuits but are not composed of logic gates and flip-flops. This necessitates different fault models and test techniques for memory blocks.

In memory technology, the capacity quadruples roughly every 3 years [1], which leads to decrease in memory price per bit (being stored). It is to be noted that increase in capacity does not lead to a proportional rise in area of a memory chip. In other words, high storage capacity is obtained by raise in density, which implies decrease in the size of circuit (capacitor) used to store a bit. Experiments with new materials having high dielectric constant like barium strontium titanate [2] are being done that facilitate greater capacitance to be maintained in the same physical space. Also, design and layout techniques like stacked capacitors are being tried to achieve higher density. Further, for faster access of the memory, various methods are being developed which includes fast page mode (FP), extended data output ( EDO ), synchronous DRAM (SDRAM), double data rate etc.

So, modern memory designs aim at high capacity at lower area and fast access speed. This leads to a situation where we have very less charge stored per memory cell (because of low capacitance), and cells are extremely close to each other. Further, due to use of deep micron technology the cells are becoming more susceptible to manufacturing defects.

So, unlike normal circuits where we generally do not have faults (or chips having faults are discarded), multiple faults will be present in any memory chip . In other words, the yield of memory chips would be nearly 0%, since every chip has defects. During manufacturing test, the faults are not only to be detected but also their locations (in terms of cell number) are to be diagnosed. As almost all memories will have faults in some cells, there are redundant (extra) cells in the memory. One a fault is diagnosed, the corresponding cell is disconnected and a new fault free cell is connected in the appropriate position. This replacement is achieved by blowing fuses (using laser) to reroute defective cells to normal spare cells.

•  The sole functionality of a cell is to sore a bit information which is implemented using a capacitor; when the capacitor is charged it represents 1 and when there is no charge it represents 0. No logic gates are involved in a memory. Use of logic gates (in flip-flops) instead of capacitors to store bit information would lead to a very large area.

The above two points basically differentiate testing of logic gate circuits from memory.

So, new fault models and test procedures are required for testing memories. In this lecture we will study the most widely used fault models and test techniques for such fault models in memories.