References

• Samir Palnitkar, “Verilog HDL: a guide to digital design and synthesis”, 2 nd Edition, Prentice Hall Press, 2003

• Peter J. Ashenden, “The Designer's Guide to VHDL”, 2 nd Edition, Morgan Kaufmann Publishers Inc., 2001

• Wolfgang Muller, Wolfgang Rosenstiel and Jurgen Ruf, “SystemC: methodologies and applications”, 1 st Edition, Kluwer Academic Publishers, 2003.

• S.Amellal and B.Kaminska. ”A CDFG model for synthesis from VHDL”. Technical report, Ecole Polytechnique de Montreal, August 1997.

• Gjalt G. de Jong, “Data flow graphs: system specification with the most unrestricted semantics”, Proceedings of the conference on European design automation, pages 401--405, 1991.

• R. Camposano and R. M. Tabet, “Design representation for the synthesis of behavioral VHDL models”, Symposium on Computer Hardware Description Languages and Their Applications, page 49 - 58, 1989.

• D. Gajski and L. Ramachandran, “Introduction to high-level synthesis”, IEEE Design and Test of Computers, Vol. 11, No. 4, page 44-54, 1994.