Module 5 : Power Disipation in CMOS Circuits
Lecture 26 : Power Disipation in CMOS Circuits
 
26.8 Short-Circuit Power Dissipation
The short-circuit power dissipation is given by
pd (Eq 26.13)
For the input waveform shown in Fig 26.81a, which depicts the short-circuit (Fig26.81b) in an unloaded inverter,
Imean (Eq 26.14)
assuming that Vt and Beta and that the behavior is symmetrical around t2.
imean
with
vin
t1
t2
 
scpwd
 
Thus for an inverter without load, assuming that tr ,
psc
where tp is the period of the waveform. This derivation is for an unloaded inverter. It shows that the short-circuit current is dependent on beta and the input waveform rise and fall times. Slow rise times on nodes can result in significant (20%) short-circuit power dissipation for loaded inverters. Thus it is good practice to keep all edges fast if power dissipation is a concern. As the load capacitance is increased the signifance of the short-circuit dissipation is reduced by the capacitive dissipation Pd.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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