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| 26.7 Methods To Reduce Dynamic Power Dissipation |
As can be seen from Eq (26.12), the power dissipated can be reduced by reducing either the clock frequency,  , or the load capacitance,  , or the rail voltage,  , or the switching activity parameter,  . |
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| Reducing the clock frequency is the easiest thing to do, but it seriously affects the performance of the chip. Applications where power is paramount, this is approach can be used satisfactorily. |
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| Another method to reduce the dissipated power is to lower the load capacitance, . But this method is more difficult than the previous approach because it involves conscientious system design, so that there are fewer wires, smaller pins, smaller fan-out, smaller devices etc. |
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| Power dissipation can also be reduced by reducing the rail voltage, . But this can be done only through device technology. Also rail voltage is a standard agreed to in many cases by the semiconductor industry, hence we do not have much control over this parameter. Also rail voltage is strongly dependent on the threshold voltage and the noise margin. |
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| Some special techniques are also used to reduce power dissipation. The first one involves the use of pipelining to operate the internal logic at a lower clock than the i/o frequency. The other technique is to reduce switching activity, , by optimizing algorithms, architecture, logic topology and using special encoding techniques. |
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