Module 5 : Power Disipation in CMOS Circuits
Lecture 26 : Power Disipation in CMOS Circuits
 
26.6 Dynamic Power Dissipation
During switching, either from '0' to '1' or, alternatively, from '1' to '0', both n- and p-transistors are on for a short period of time. This results in a short current pulse from Vdd to Vss. Current is also required to charge and discharge the output capacitive load. This latter term is usually the dominant term. The current pulse from Vdd to Vss results in a 'short-circuit' dissipation that is dependent on the input rise/fall time, the load capacitance and the gate design.
chdisch
Fig 26.61: Power dissipation due to charging/discharging of capacitor
 
The dynamic dissipation can be modeled by assuming that the rise and fall time of the step input is much less than the repetition period. The average dynamic power, Pd , dissipated during switching for a square-wave input, Vin, having a repetition frequency of fp, is given by
pd (Eq 26.8)
where
in = n-device transient current
ip = p-device transient current
 
For a step input and with int
pd (Eq 26.9)
pd (Eq 26.10)
with fp,
resulting in
pd (Eq 26.11)
 
Thus for a repetitive step input the average power that is dissipated is proportional to the energy required to charge and discharge the circuit capacitance. The important factor to be noted here is that Eq 26.11 shows power to be proportional to switching frequency but independent of device parameters.
The power dissipation also depends on the switching activity, denoted by, alpha.
The equation can then can be written as
pd (Eq 26.12)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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