Figure 14. Example of deductive fault simulation with input I1=1 (Inputs of the AND gate are 0 and 1)
Based on the discussion of Example 11 through example 14, the following table (Table 5) can be constructed that enumerates the rules for all logic gates required for fault deduction.
Table 5. Fault deduction rules for logic gates
This table is for 2 input gates only, however, these rules can be directly extended for 3 or more input gates. For example, for a 3 input AND gate (In1, In2, In3), with In1=1, In2=1, In3=1, the rule for deduction is 
while for In1=1, In2=1, In3=0, the rule for deduction is 
.
Figure 15. Deductive fault simulation with input I1=1 and I2=1