References

1.  A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, UK: John Wiley & Sons, Inc., 1991.

2. P. Mazumder and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories. Boston: Kluwer Academic Publishers, 1996.

3. Ashok K. Sharma, “Advanced Semiconductor Memories: Architectures, Designs, and Applications”, Wiley-IEEE Press, 2002.

4.  R. Nair, S. M. Thatte, and J. A. Abraham, “Efficient Algorithms for Testing Semiconductor Random-Access Memories,” IEEE Trans. on Computers, vol. C-28, no. 3, pp. 572–576, Mar. 1978.

5.  S. M. Thatte and J. A. Abraham, “Testing of Semiconductor Random Access Memories,” in Proc. of the International Fault-Tolerant Computing Symp., June 1977, pp. 81–87.

6.  Ashok K. Sharma, “Semiconductor Memories: Technology, Testing, and Reliability”, Wiley-IEEE Press, 2002

7.  D. S. Suk and S. M. Reddy, “A March Test for Functional Faults in Semiconductor Random-Access Memories,” IEEE Trans. on Computers, vol. C-30, no. 12, pp. 982– 985, Dec. 1981.

8.  K. Kinoshita and K. K. Saluja, “Built-in Testing of Memory Using On-Chip Compact Testing Scheme,” in Proc. of the International Test Conf., Oct. 1984, pp. 271–281.

9.  K. Kinoshita and K. K. Saluja, ”Built-in Testing of Memory Using an On-Chip Compact Testing Scheme,” IEEE Trans. on Computers, vol. C-35, no. 10, pp. 862–870, Oct. 1986.

10.  P. Mazumder and K. Chakraborty, Testing and Testable Design of High-Density Random-Access Memories. Boston: Kluwer Academic Publishers, 1996.