Module 11 :Built in Self test (BIST)

Lecture 3 and 4:Memory Testing

•  Example of testing active NPSF

(i) write 0,1,0,0 in cell no. 0,2,3,4 respectively, of the type-1 neighborhood (of the cell under test) and read back the values, (ii) write 1 in cell under test and read back the value, (iii) write 0 in cell 2 and (iv) read the value in cell under test (which is to be 1).

•  Example of testing passive NPSF

(i) write 0,0,0,0 in cell no. 0,2,3,4 respectively, of the type-1 neighborhood (of the cell under test) and read back the values, (ii) write 0 in cell under test and read back the value, (iii) write 1 in cell under test and (iv) read the value in cell under test (which is to be 1).


3.6  Address decoder faults

A little variation of March test (given in Figure 12 and Figure 13) can test all four address decoder faults given in Section 2.6. We will only give the test sequence (of modified March test) and proof idea that it tests all four address decoder faults. The formal proof is given in [1].

The test pattern sequence for modified March test is given below.

•  In increasing order of address of the memory cells, read the value of the memory cells and write complement value in the cell. If 1 is read at cell 0, value of 1 is written to cell 0; following that same procedure is followed for cell 2 and so on for entire memory.

•  In decreasing order of address of the memory cells, read the cells (match with expected value) and write complement value in the cell.

The basic principle is that as the memory writing and examination operation moves through memory, any address decoder fault that causes unexpected accesses of memory locations will cause those locations to be written to an unexpected value. As the test proceeds, it will discover those locations and report a fault.

4. Basics of memory BIST

From the discussion in last section it may be noted that for March test an address generator (increasing and decreasing order) and a data reader cum writer is required. So BIST for March test will be simply an LFSR and a data reader cum writer. As in the case of logic BIST, the LFSR should have primitive polynomial (so that it generates all numbers from 1 to 2n ), and along with this the LFSR for memory BIST should the following features

•  Be able to generate all the 0 pattern to access the last memory location

•  Be able to generate forward and reverse order patterns i.e., if 1-0-2-3 be the sequence of the LFSR (when initialized with 1) then there should be a mode to generate the sequence 1-3-2-0.

It may be noted that March test can be modified by replacing “sequential read/write” with “arbitrary order read/write, but covering all cells” without loss in test capability. In other words, in Figure 12 and Figure 13, we illustrated cell traversal from 0 to 9 and then from 9 to 0. However, the test capability will not change if sequence of cell traversal is any other sequence, for example, 1-0-2-5-7-3-4-6-9-8 while moving in ascending order and 1-8-9-6-4-3-7-5-2-0 in reverse order.

In this section we will discuss LFSR design that satisfies the above mentioned two points which can be used for test pattern sequence generation in March test. BIST circuitry for testing faults that involve participation of more than one cell like coupling faults, NPSFs etc. are more complex and will not be covered in this lecture; for details the student is referred to [8,9].

We will modify the standard LFSR discussed in Figure 4 of Lecture 1 of this module (Module XIII) so that it satisfies the above mentioned two points for memory BIST; Figure 15 illustrates the modified LFSR, where the positions of the flip-flops are in reverse order, i.e., X0 (LFSR of Figure 4 of Lecture 1) is marked as X2and X2(LFSR of Figure 4 of Lecture 1) is marked as X0. Also, circuitry for feedback from last flip-flop to first flip-flop now involves an extra XOR gate and a NOR gate. It may be noted from the sequence of outputs of Figure 15 that the all-0 pattern is generated from the pattern because of the extra NOR+XOR gates. If the circuitry for feedback from last flip-flop to first flip-flop comprises only XOR gates (as in LFSR of Figure 4 of Lecture 1), then the all-0 pattern cannot be generated from any pattern in (except ). If we start from the all-0 pattern in the LFSR of Figure 4 of Lecture 1 it does not change its output.