Figure 15 LFSR to generate up address sequence for memory BIST
The output sequence generated by the LFSR of Figure 15 is given below.
It may be noted that the LFSR generates all patterns in the range 
along with the 000 pattern. The seed of the LFSR is 001. The pattern sequence in decimal is 1-0-4-6-7-3-5-2.
As already discussed, for March test the LFSR (Figure 15) should also have a counterpart that can generates a reverse pattern i.e., the reverse LFSR should generate reverse of “1-0-4-6-7-3-5-2”, which is 1-2-5-3-7-6-4-0 (seed is assumed to be same for both the LFSR and its reverse counterpart). Broadly speaking, the reverse LFSR should shift the data in the reverse direction. So to achieve this reverse shift of data, the D and Q terminals are to be swapped in the (forward) LFSR and numbering of the flip-flops is to be made in reverse order. The feedback from last flip-flop to the first one will also have the XOR-NOR gate circuitry (as in the case of forward LFSR) to generate the all-0 sequence. Figure 16 shows the reverse LFSR (for the forward one shown in Figure 15).
Figure 16. Reverse LFSR of the (forward) LFSR in Figure 15
The output sequence generated by the LFSR of Figure 16 is given below.
A broad architecture for memory BIST using LFSR is shown in Figure 17. The various blocks are explained as follows
- LFSR: The LFSR block comprises both forward and reverse LFSRs. This block is used to generate address of the memory cells where read/write is to be done
- Data: The data block to writes 0 and 1 in the cells as per steps of March test.
- Equality comparator: In general, most of the ICs have their memory divided into have multiple arrays (or memory blocks). In such a case we can test two or more arrays (in this case 2) simultaneously, by applying the same addresses and data (being written, as per March test) to all the arrays. If same address and data is applied, outputs of all the memory blocks are to be same. The mutual comparator ensures that outputs of all blocks are equal and asserts the error signal when output of some block disagrees with that of others. The comparator eliminates the need to generate the good machine response, response compaction etc.
• Controller: It basically coordinates the BIST procedure. It selects forward LFSR and backward LFSR alternatively to generate address for memory cells. It also enables the data writer block to write 0 and 1 as per steps of March test. Further, it also enables the equality comparator to check if outputs of all memory blocks are equal.