Figure 17. Memory BIST using LFSR

5.Conclusions

All the lectures covered in the Digital Testing module except, the present one were focused on testing of digital circuits comprising Boolean gates and flip-flops. However, memory is a very vital element for digital circuits. The structure of memory blocks are basically different compared to logic blocks. In this lecture we have covered simple logical fault models applicable to digital memories and the corresponding test procedures. Also we have given a brief idea about BIST of memories for March test.

Most of the discussions in this lecture were focused at logical fault models in memory which are independent of the fabrication technology, their physical layout, electrical parameters etc. The advantage of logical models is that they have enough detail to adequately model a good number of faults like stuck-at, transition, coupling, etc. and at the same time simple to handle. However, in memory blocks fabricated with latest technologies we need to test for more advanced type of faults which are based on timing parameters, geometry of the layout etc. Timing tests are required to validate the read/write speed of the memory block as per specifications. The geometrical fault model of a memory requires complete knowledge of the chip layout. This allows inductive fault analysis [10] to be used during initial memory chip production when we are trying to redesign the memory layout to increase the memory chip yield. The details of memory testing for advanced fault models can be found in [1,6,10].