Questions and Answers
• How can test time be reduced for the circuit with scan chain of Figure 14 of this lecture?
Answer:
The circuit in Figure 14 has a single scan chain with three flip-flops. So time taken to set/reset all the flip-flops is three clock pulses. To save test time the scan chain can be divided into multiple sub-chains with separate Scan in and Scan out pins. In this case we have divided the chain into 2 parts—one has F1 and F2 and the second has F3 only. So we have two sets of Scan in and Scan out pins. The design is illustrated in the figure below. Now both the chains can be loaded concurrently. So, only two clock pulses are required to set/reset all the flip-flops.
2. How can the flip-flops themselves be tested in a scan chain based testing?
Answer:
An advantage of scan chain based testing over time frame expansion and shift register technique is the ability to test the flip-flops in the circuit under test. A toggle sequence, 00110011 . . ., of length nff + 4 , where nff is the total number of flip-flops, is applied at Scan in. This sequence produces all four transitions 0→0, 0→1, 1→1 and 1→1 in all the flip-flops. The sequence is brought out through the Scan out pin. So if a correct toggle sequence is observed in the Scan out pin, then the flip-flops are working normally. It is shown in stuck at fault model that toggle sequence covers almost all stuck at faults in the flip-flops.