The procedure of testing the circuit of Figure 18(c) using partial scan is shown in Figure 19. As shown in Figure 19(a), net i is set to 1 by making M=1 and applying 1 in Scan in input with a clock pulse; F2 is set using scan chain. Now (Figure 19(b)) net d is set to 1 by making M=0 and applying 1 in primary input c with a clock pulse; F1 is set using time frame expansion. Finally after setting the flip-flops, test pattern a =1, b =1, c =X is applied, which sensitizes and propagates the fault effect to the output k.

6. Conclusions

In the combined two lectures we have seen testing of sequential circuits with design for testability techniques, namely set/reset lines, shift register with set/reset lines, scan chain and partial scan chain. Design for testability is additional resources like circuitry or I/O pins used to make testing easier. Among all the techniques, we saw that partial scan is the most efficient one as it uses additional resources only when testing becomes infeasible due to cyclic parts in a circuit. However, sometimes non-cyclic flip-flops are also made scan enabled (in partial scan technique) to minimize ATPG time; as shown in Figure 17 of this lecture, propagating fault effects by scan chains minimize ATPG effort. Another direction called “multiple chains” is taken to minimize test time in scan chain based techniques. In this scheme, instead of a single scan chain, the chain is broken into multiple parts. The start of each chain is brought out as separate Scan in and end of the chain is brought out as separate Scan out. This increases the number of I/Os, but all the smaller chains can be fed with bits values concurrently, minimizing test time.