| Module Name | Download |
|---|---|
| Week_01_Assignment_01 | Week_01_Assignment_01 |
| Week_02_Assignment_02 | Week_02_Assignment_02 |
| Week_03_Assignment_03 | Week_03_Assignment_03 |
| Week_04_Assignment_04 | Week_04_Assignment_04 |
| Week_05_Assignment_05 | Week_05_Assignment_05 |
| Week_06_Assignment_06 | Week_06_Assignment_06 |
| Week_07_Assignment_07 | Week_07_Assignment_07 |
| Week_08_Assignment_08 | Week_08_Assignment_08 |
| Week_09_Assignment_09 | Week_09_Assignment_09 |
| Week_10_Assignment_10 | Week_10_Assignment_10 |
| Week_11_Assignment_11 | Week_11_Assignment_11 |
| Week_12_Assignment_12 | Week_12_Assignment_12 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Outline - What is Synthesis? | Download |
| 2 | Chip Design Flow and Hardware Modelling | Download |
| 3 | VHDL: Introduction to Hardware Description Languages & VHDL Basics | Download |
| 4 | VHDL: Modelling Timing - Events & Transactions | Download |
| 5 | VHDL: Specifying Hardware Behaviour with Processes | Download |
| 6 | VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries | Download |
| 7 | Introduction to High-level Synthesis | Download |
| 8 | Language front-end Design Representation | Download |
| 9 | Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, & Strength Reduction | Download |
| 10 | Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination & Loop Invariant Code Motion | Download |
| 11 | Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining | Download |
| 12 | Hardware Transformations & ASAP / ALAP Scheduling | Download |
| 13 | Scheduling in High Level Synthesis: List Scheduling & Time-constrained Scheduling | Download |
| 14 | Force Directed Scheduling & Register Allocation | Download |
| 15 | High Level Synthesis and Timing Issues | Download |
| 16 | Finite State Machine Synthesis: Introduction to FSM Encoding | Download |
| 17 | Finite State Machine Synthesis: Identifyinh Common Cubes & Graph Embedding | Download |
| 18 | The Retiming Problem | Download |
| 19 | Efficient Solution to Retiming & Introduction to Logic Synthesis | Download |
| 20 | Binary Decision Diagrams | Download |
| 21 | Introduction to Logic Synthesis | Download |
| 22 | Two-level Logic Optimisation | Download |
| 23 | Multi-Level Logic Optimisation | Download |
| 24 | Multi-level Logic Synthesis: Technology Mapping | Download |
| 25 | Introduction to Timing Analysis | Download |
| 26 | Timing Analysis & Critical Paths | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Outline - What is Synthesis? | Download To be verified |
| 2 | Chip Design Flow and Hardware Modelling | Download To be verified |
| 3 | VHDL: Introduction to Hardware Description Languages & VHDL Basics | Download To be verified |
| 4 | VHDL: Modelling Timing - Events & Transactions | Download To be verified |
| 5 | VHDL: Specifying Hardware Behaviour with Processes | Download To be verified |
| 6 | VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries | Download To be verified |
| 7 | Introduction to High-level Synthesis | Download To be verified |
| 8 | Language front-end Design Representation | Download To be verified |
| 9 | Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, & Strength Reduction | Download To be verified |
| 10 | Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination & Loop Invariant Code Motion | Download To be verified |
| 11 | Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining | Download To be verified |
| 12 | Hardware Transformations & ASAP / ALAP Scheduling | Download To be verified |
| 13 | Scheduling in High Level Synthesis: List Scheduling & Time-constrained Scheduling | Download To be verified |
| 14 | Force Directed Scheduling & Register Allocation | Download To be verified |
| 15 | High Level Synthesis and Timing Issues | Download To be verified |
| 16 | Finite State Machine Synthesis: Introduction to FSM Encoding | Download To be verified |
| 17 | Finite State Machine Synthesis: Identifyinh Common Cubes & Graph Embedding | Download To be verified |
| 18 | The Retiming Problem | Download To be verified |
| 19 | Efficient Solution to Retiming & Introduction to Logic Synthesis | Download To be verified |
| 20 | Binary Decision Diagrams | Download To be verified |
| 21 | Introduction to Logic Synthesis | Download To be verified |
| 22 | Two-level Logic Optimisation | Download To be verified |
| 23 | Multi-Level Logic Optimisation | Download To be verified |
| 24 | Multi-level Logic Synthesis: Technology Mapping | Download To be verified |
| 25 | Introduction to Timing Analysis | Download To be verified |
| 26 | Timing Analysis & Critical Paths | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |