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| 33.1 Introduction |
| Pad cells surround the rectangular metal patches where external bonds are made. Pads must be sufficiently large and sufficiently spaced apart from each other. There are three types of pad cells, input, output, power (also, tristate, analog). Typical structures inside pad cells should have |
- sufficient connection area (eg. 85 x 85 microns) in the pad,
- electrostatic discharge (ESD) protection structures
- interface to internal circuitry
- circuitry specific to input and output pads
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| Pads are generally arranged around the chip perimeter in a "pad frame". Pad frame will have a signal ring of pads in smaller designs. Lower limit on pad size is minimum size to which a bond wire can be attached; typically 100-150 micrometers. It is also a minimum pitch at which bonding machines can operate. |
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| Input pads of gates of input buffer transistors are susceptible to high voltage build up, so we need to have ESD protection for it. Output pads are expected to drive large capacitance loads, so characteristics of load must be met by proper sizing of output buffer. Due to large transistors, I/O currents are higher and hence Latch-Up may occur. To prevent this, we use guard rings in layout. For area efficiency, I/O transistors should be constructed from several small transistors in parallel. Long gates must be provided to reduce avalanche breakdown tendency. |
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