The output is ‘high’ and no current is drawn from the supply.
As we raise the input just above VTn, the output starts falling.
In this region the nMOS is saturated, while the pMOS is linear.
17.7
nMOS saturated, pMOS linear
The input voltage is assumed to be sufficiently low so that the output voltage exceeds the saturation voltage Vi - VTn. Normally, this voltage will be higher than VTp, so the p channel transistor is in linear mode of operation.
Equating currents through the n and p channel transistors, we get
we get
