17.7 |
nMOS saturated, pMOS linear (contd..) |
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The solutions are:
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substituting the values of V1 and V2 and choosing the sign which puts V0 in the correct range, we get
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As the input voltage is increased, the output voltage will decrease.
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The output voltage will fall below
Vi - VTnwhen |
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The nMOS is now in its linear mode of operation. The derived equation does not apply beyond this input voltage.
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