Module 4 : Propagation Delays in MOS
Lecture 17 : Pseudo NMOS Inverter
 
17.1 Introduction
The inverter that uses a p-device pull-up or load that has its gate permanently ground. An n-device pull-down or driver is driven with the input signal. This roughly equivalent to use of a depletion load is Nmos technology and is thus called ‘Pseudo-NMOS’. The circuit is used in a variety of CMOS logic circuits. In this, PMOS for most of the time will be linear region. So resistance is low and hence RC time constant is low. When the driver is turned on a constant DC current flows in the circuit.
Fig 17.1: CMOS Inverter Circuit
 
17.2 Different Configurations with NMOS Inverter
Cascade pseudo NMOS invertor: Saturated n-mosNMOS invertor: More saturated NMOS Load invertor:
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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