| Module Name | Download |
|---|---|
| Week_01_Assignment_01 | Week_01_Assignment_01 |
| Week_02_Assignment_01 | Week_02_Assignment_01 |
| Week_03_Assignment_01 | Week_03_Assignment_01 |
| Week_04_Assignment_01 | Week_04_Assignment_01 |
| Week_05_Assignment_01 | Week_05_Assignment_01 |
| Week_06_Assignment_01 | Week_06_Assignment_01 |
| Week_07_Assignment_01 | Week_07_Assignment_01 |
| Week_09_Assignment_01 | Week_09_Assignment_01 |
| Week_10_Assignment_01 | Week_10_Assignment_01 |
| Week_11_Assignment_01 | Week_11_Assignment_01 |
| Week_12_Assignment_01 | Week_12_Assignment_01 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Introduction: Objectives and Pre-requisites | Download |
| 2 | Review of digital logic | Download |
| 3 | Timing and Power in digital circuits | Download |
| 4 | Implementation Costs and Metrics | Download |
| 5 | Example: Audio processing | Download |
| 6 | Example: AlexNet | Download |
| 7 | Architecture cost components | Download |
| 8 | Examples of Architectures | Download |
| 9 | Multi-objective Optimization | Download |
| 10 | Number representation | Download |
| 11 | Scientific notation and Floating point | Download |
| 12 | Basic FIR filter | Download |
| 13 | Serial FIR filter architectures | Download |
| 14 | Simple programmable architecture | Download |
| 15 | Block diagrams and SFGs | Download |
| 16 | Dataflow Graphs | Download |
| 17 | Iteration period | Download |
| 18 | FIR filter iteration period | Download |
| 19 | IIR filter iteration period | Download |
| 20 | Computation Model | Download |
| 21 | Constraint analysis for IPB computation | Download |
| 22 | Motivational examples for IPB | Download |
| 23 | General IPB computation | Download |
| 24 | Sample period calculation | Download |
| 25 | Parallel architecture | Download |
| 26 | Odd-even register reuse | Download |
| 27 | Power consumption | Download |
| 28 | Pipelining | Download |
| 29 | Pipelining FIR filter | Download |
| 30 | Time-invariant systems | Download |
| 31 | Valid pipelining examples | Download |
| 32 | Feedforward cutsets | Download |
| 33 | Balanced pipeline | Download |
| 34 | Retiming basic concept | Download |
| 35 | Example and uses of retiming | Download |
| 36 | Resource sharing: adder example | Download |
| 37 | Changing iteration period | Download |
| 38 | Hardware assumptions and constraint analysis | Download |
| 39 | Mathematical formulation | Download |
| 40 | Examples with formulation | Download |
| 41 | Example: Biquad filter | Download |
| 42 | Hardware architecture | Download |
| 43 | Review biquad folding sets | Download |
| 44 | Complete biquad hardware | Download |
| 45 | DEMO: FFT in Vivado HLS | Download |
| 46 | DEMO: FFT synthesis | Download |
| 47 | Obtaining a folding schedule | Download |
| 48 | ASAP schedule | Download |
| 49 | Utilization Efficiency | Download |
| 50 | ALAP schedule | Download |
| 51 | Iteration period bound and scheduling | Download |
| 52 | Retiming for scheduling | Download |
| 53 | Blocked schedules | Download |
| 54 | Overlapped schedules | Download |
| 55 | Improved blocked schedule | Download |
| 56 | Allocation, Binding and Scheduling | Download |
| 57 | DEMO: Analyze FFT implementation | Download |
| 58 | DEMO: FFT interface | Download |
| 59 | Scheduling: problem formulation | Download |
| 60 | Example: differential equation solver | Download |
| 61 | Heuristic approaches to scheduling | Download |
| 62 | Mathematical formulation | Download |
| 63 | ILP formulation | Download |
| 64 | List scheduling | Download |
| 65 | Hardware model | Download |
| 66 | Force Directed Scheduling | Download |
| 67 | DEMO: HLS on FFT | Download |
| 68 | DEMO: FFT Simulation and Optimization | Download |
| 69 | DEMO: CPU interfacing | Download |
| 70 | Software Compilation | Download |
| 71 | Optimization Examples | Download |
| 72 | Loop optimizations 1 | Download |
| 73 | Loop optimizations 2 | Download |
| 74 | Loop optimizations 3 | Download |
| 75 | Software pipelining 1 | Download |
| 76 | Software pipelining 2 | Download |
| 77 | FFT Optimization | Download |
| 78 | Demo: Vivado setup | Download |
| 79 | Background: CPUs and FPGAs | Download |
| 80 | Demo: Vivado HLS FFT IP Export | Download |
| 81 | Demo: Vivado ILA and VIO on hardware | Download |
| 82 | Demo: FFT on FPGA board | Download |
| 83 | Demo: Simulating SoC and SDK | Download |
| 84 | Background: Understanding ELF files | Download |
| 85 | On-chip communication basics | Download |
| 86 | Many-to-Many communication | Download |
| 87 | AXI bus handshaking | Download |
| 88 | AXI bus (contd) | Download |
| 89 | Demo: Microblaze processor on FPGA | Download |
| 90 | Demo: Performance counter AXI peripheral | Download |
| 91 | Demo: HW accelerator for FPGA | Download |
| 92 | DMA and arbitration | Download |
| 93 | Network-on-chip basics | Download |
| 94 | NoC - topologies and metrics | Download |
| 95 | NoC - routing | Download |
| 96 | NoC - switching and flow control | Download |
| 97 | Systolic Arrays - Background | Download |
| 98 | Systolic Arrays - Examples | Download |
| 99 | CORDIC algorithm | Download |
| 100 | Parallel implementation of FIR filters | Download |
| 101 | Unfolding Transformation | Download |
| 102 | Lookahead Transformation | Download |
| 103 | Introduction to GPUs and Matrix multiplication | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction: Objectives and Pre-requisites | Download To be verified |
| 2 | Review of digital logic | Download To be verified |
| 3 | Timing and Power in digital circuits | Download To be verified |
| 4 | Implementation Costs and Metrics | Download To be verified |
| 5 | Example: Audio processing | Download To be verified |
| 6 | Example: AlexNet | Download To be verified |
| 7 | Architecture cost components | Download To be verified |
| 8 | Examples of Architectures | Download To be verified |
| 9 | Multi-objective Optimization | Download To be verified |
| 10 | Number representation | Download To be verified |
| 11 | Scientific notation and Floating point | Download To be verified |
| 12 | Basic FIR filter | Download To be verified |
| 13 | Serial FIR filter architectures | Download To be verified |
| 14 | Simple programmable architecture | Download To be verified |
| 15 | Block diagrams and SFGs | Download To be verified |
| 16 | Dataflow Graphs | Download To be verified |
| 17 | Iteration period | Download To be verified |
| 18 | FIR filter iteration period | Download To be verified |
| 19 | IIR filter iteration period | Download To be verified |
| 20 | Computation Model | Download To be verified |
| 21 | Constraint analysis for IPB computation | PDF unavailable |
| 22 | Motivational examples for IPB | PDF unavailable |
| 23 | General IPB computation | PDF unavailable |
| 24 | Sample period calculation | PDF unavailable |
| 25 | Parallel architecture | PDF unavailable |
| 26 | Odd-even register reuse | PDF unavailable |
| 27 | Power consumption | PDF unavailable |
| 28 | Pipelining | PDF unavailable |
| 29 | Pipelining FIR filter | PDF unavailable |
| 30 | Time-invariant systems | PDF unavailable |
| 31 | Valid pipelining examples | PDF unavailable |
| 32 | Feedforward cutsets | PDF unavailable |
| 33 | Balanced pipeline | PDF unavailable |
| 34 | Retiming basic concept | PDF unavailable |
| 35 | Example and uses of retiming | PDF unavailable |
| 36 | Resource sharing: adder example | PDF unavailable |
| 37 | Changing iteration period | PDF unavailable |
| 38 | Hardware assumptions and constraint analysis | PDF unavailable |
| 39 | Mathematical formulation | PDF unavailable |
| 40 | Examples with formulation | PDF unavailable |
| 41 | Example: Biquad filter | PDF unavailable |
| 42 | Hardware architecture | PDF unavailable |
| 43 | Review biquad folding sets | PDF unavailable |
| 44 | Complete biquad hardware | PDF unavailable |
| 45 | DEMO: FFT in Vivado HLS | PDF unavailable |
| 46 | DEMO: FFT synthesis | PDF unavailable |
| 47 | Obtaining a folding schedule | PDF unavailable |
| 48 | ASAP schedule | PDF unavailable |
| 49 | Utilization Efficiency | PDF unavailable |
| 50 | ALAP schedule | PDF unavailable |
| 51 | Iteration period bound and scheduling | PDF unavailable |
| 52 | Retiming for scheduling | PDF unavailable |
| 53 | Blocked schedules | PDF unavailable |
| 54 | Overlapped schedules | PDF unavailable |
| 55 | Improved blocked schedule | PDF unavailable |
| 56 | Allocation, Binding and Scheduling | PDF unavailable |
| 57 | DEMO: Analyze FFT implementation | PDF unavailable |
| 58 | DEMO: FFT interface | PDF unavailable |
| 59 | Scheduling: problem formulation | PDF unavailable |
| 60 | Example: differential equation solver | PDF unavailable |
| 61 | Heuristic approaches to scheduling | PDF unavailable |
| 62 | Mathematical formulation | PDF unavailable |
| 63 | ILP formulation | PDF unavailable |
| 64 | List scheduling | PDF unavailable |
| 65 | Hardware model | PDF unavailable |
| 66 | Force Directed Scheduling | PDF unavailable |
| 67 | DEMO: HLS on FFT | PDF unavailable |
| 68 | DEMO: FFT Simulation and Optimization | PDF unavailable |
| 69 | DEMO: CPU interfacing | PDF unavailable |
| 70 | Software Compilation | PDF unavailable |
| 71 | Optimization Examples | PDF unavailable |
| 72 | Loop optimizations 1 | PDF unavailable |
| 73 | Loop optimizations 2 | PDF unavailable |
| 74 | Loop optimizations 3 | PDF unavailable |
| 75 | Software pipelining 1 | PDF unavailable |
| 76 | Software pipelining 2 | PDF unavailable |
| 77 | FFT Optimization | PDF unavailable |
| 78 | Demo: Vivado setup | PDF unavailable |
| 79 | Background: CPUs and FPGAs | PDF unavailable |
| 80 | Demo: Vivado HLS FFT IP Export | PDF unavailable |
| 81 | Demo: Vivado ILA and VIO on hardware | PDF unavailable |
| 82 | Demo: FFT on FPGA board | PDF unavailable |
| 83 | Demo: Simulating SoC and SDK | PDF unavailable |
| 84 | Background: Understanding ELF files | PDF unavailable |
| 85 | On-chip communication basics | PDF unavailable |
| 86 | Many-to-Many communication | PDF unavailable |
| 87 | AXI bus handshaking | PDF unavailable |
| 88 | AXI bus (contd) | PDF unavailable |
| 89 | Demo: Microblaze processor on FPGA | PDF unavailable |
| 90 | Demo: Performance counter AXI peripheral | PDF unavailable |
| 91 | Demo: HW accelerator for FPGA | PDF unavailable |
| 92 | DMA and arbitration | PDF unavailable |
| 93 | Network-on-chip basics | PDF unavailable |
| 94 | NoC - topologies and metrics | PDF unavailable |
| 95 | NoC - routing | PDF unavailable |
| 96 | NoC - switching and flow control | PDF unavailable |
| 97 | Systolic Arrays - Background | PDF unavailable |
| 98 | Systolic Arrays - Examples | PDF unavailable |
| 99 | CORDIC algorithm | PDF unavailable |
| 100 | Parallel implementation of FIR filters | PDF unavailable |
| 101 | Unfolding Transformation | PDF unavailable |
| 102 | Lookahead Transformation | PDF unavailable |
| 103 | Introduction to GPUs and Matrix multiplication | PDF unavailable |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |