Modules / Lectures
Module NameDownload

Sl.No Chapter Name MP4 Download
1Introduction: Objectives and Pre-requisitesDownload
2Review of digital logicDownload
3Timing and Power in digital circuitsDownload
4Implementation Costs and MetricsDownload
5Example: Audio processingDownload
6Example: AlexNetDownload
7Architecture cost componentsDownload
8Examples of ArchitecturesDownload
9Multi-objective OptimizationDownload
10Number representationDownload
11Scientific notation and Floating pointDownload
12Basic FIR filterDownload
13Serial FIR filter architecturesDownload
14Simple programmable architectureDownload
15Block diagrams and SFGsDownload
16Dataflow GraphsDownload
17Iteration periodDownload
18FIR filter iteration periodDownload
19IIR filter iteration periodDownload
20Computation ModelDownload
21Constraint analysis for IPB computationDownload
22Motivational examples for IPBDownload
23General IPB computationDownload
24Sample period calculationDownload
25Parallel architectureDownload
26Odd-even register reuseDownload
27Power consumptionDownload
29Pipelining FIR filterDownload
30Time-invariant systemsDownload
31Valid pipelining examplesDownload
32Feedforward cutsetsDownload
33Balanced pipelineDownload
34Retiming basic conceptDownload
35Example and uses of retimingDownload
36Resource sharing: adder exampleDownload
37Changing iteration periodDownload
38Hardware assumptions and constraint analysisDownload
39Mathematical formulationDownload
40Examples with formulationDownload
41Example: Biquad filterDownload
42Hardware architectureDownload
43Review biquad folding setsDownload
44Complete biquad hardwareDownload
45DEMO: FFT in Vivado HLSDownload
46DEMO: FFT synthesisDownload
47Obtaining a folding scheduleDownload
48ASAP scheduleDownload
49Utilization EfficiencyDownload
50ALAP scheduleDownload
51Iteration period bound and schedulingDownload
52Retiming for schedulingDownload
53Blocked schedulesDownload
54Overlapped schedulesDownload
55Improved blocked scheduleDownload
56Allocation, Binding and SchedulingDownload
57DEMO: Analyze FFT implementationDownload
58DEMO: FFT interfaceDownload
59Scheduling: problem formulationDownload
60Example: differential equation solverDownload
61Heuristic approaches to schedulingDownload
62Mathematical formulation Download
63ILP formulationDownload
64List schedulingDownload
65Hardware modelDownload
66Force Directed SchedulingDownload
67DEMO: HLS on FFTDownload
68DEMO: FFT Simulation and OptimizationDownload
69DEMO: CPU interfacingDownload
70Software CompilationDownload
71Optimization ExamplesDownload
72Loop optimizations 1Download
73Loop optimizations 2Download
74Loop optimizations 3Download
75Software pipelining 1Download
76Software pipelining 2Download
77FFT OptimizationDownload
78Demo: Vivado setupDownload
79Background: CPUs and FPGAsDownload
80Demo: Vivado HLS FFT IP ExportDownload
81Demo: Vivado ILA and VIO on hardwareDownload
82Demo: FFT on FPGA boardDownload
83Demo: Simulating SoC and SDKDownload
84Background: Understanding ELF filesDownload
85On-chip communication basicsDownload
86Many-to-Many communicationDownload
87AXI bus handshakingDownload
88AXI bus (contd)Download
89Demo: Microblaze processor on FPGADownload
90Demo: Performance counter AXI peripheralDownload
91Demo: HW accelerator for FPGADownload
92DMA and arbitrationDownload
93Network-on-chip basicsDownload
94NoC - topologies and metricsDownload
95NoC - routingDownload
96NoC - switching and flow controlDownload
97Systolic Arrays - BackgroundDownload
98Systolic Arrays - ExamplesDownload
99CORDIC algorithmDownload
100Parallel implementation of FIR filtersDownload
101Unfolding TransformationDownload
102Lookahead TransformationDownload
103Introduction to GPUs and Matrix multiplicationDownload

Sl.No Chapter Name English
1Introduction: Objectives and Pre-requisitesDownload
To be verified
2Review of digital logicDownload
To be verified
3Timing and Power in digital circuitsDownload
To be verified
4Implementation Costs and MetricsDownload
To be verified
5Example: Audio processingDownload
To be verified
6Example: AlexNetDownload
To be verified
7Architecture cost componentsDownload
To be verified
8Examples of ArchitecturesDownload
To be verified
9Multi-objective OptimizationDownload
To be verified
10Number representationDownload
To be verified
11Scientific notation and Floating pointDownload
To be verified
12Basic FIR filterDownload
To be verified
13Serial FIR filter architecturesDownload
To be verified
14Simple programmable architectureDownload
To be verified
15Block diagrams and SFGsDownload
To be verified
16Dataflow GraphsDownload
To be verified
17Iteration periodDownload
To be verified
18FIR filter iteration periodDownload
To be verified
19IIR filter iteration periodDownload
To be verified
20Computation ModelDownload
To be verified
21Constraint analysis for IPB computationPDF unavailable
22Motivational examples for IPBPDF unavailable
23General IPB computationPDF unavailable
24Sample period calculationPDF unavailable
25Parallel architecturePDF unavailable
26Odd-even register reusePDF unavailable
27Power consumptionPDF unavailable
28PipeliningPDF unavailable
29Pipelining FIR filterPDF unavailable
30Time-invariant systemsPDF unavailable
31Valid pipelining examplesPDF unavailable
32Feedforward cutsetsPDF unavailable
33Balanced pipelinePDF unavailable
34Retiming basic conceptPDF unavailable
35Example and uses of retimingPDF unavailable
36Resource sharing: adder examplePDF unavailable
37Changing iteration periodPDF unavailable
38Hardware assumptions and constraint analysisPDF unavailable
39Mathematical formulationPDF unavailable
40Examples with formulationPDF unavailable
41Example: Biquad filterPDF unavailable
42Hardware architecturePDF unavailable
43Review biquad folding setsPDF unavailable
44Complete biquad hardwarePDF unavailable
45DEMO: FFT in Vivado HLSPDF unavailable
46DEMO: FFT synthesisPDF unavailable
47Obtaining a folding schedulePDF unavailable
48ASAP schedulePDF unavailable
49Utilization EfficiencyPDF unavailable
50ALAP schedulePDF unavailable
51Iteration period bound and schedulingPDF unavailable
52Retiming for schedulingPDF unavailable
53Blocked schedulesPDF unavailable
54Overlapped schedulesPDF unavailable
55Improved blocked schedulePDF unavailable
56Allocation, Binding and SchedulingPDF unavailable
57DEMO: Analyze FFT implementationPDF unavailable
58DEMO: FFT interfacePDF unavailable
59Scheduling: problem formulationPDF unavailable
60Example: differential equation solverPDF unavailable
61Heuristic approaches to schedulingPDF unavailable
62Mathematical formulation PDF unavailable
63ILP formulationPDF unavailable
64List schedulingPDF unavailable
65Hardware modelPDF unavailable
66Force Directed SchedulingPDF unavailable
67DEMO: HLS on FFTPDF unavailable
68DEMO: FFT Simulation and OptimizationPDF unavailable
69DEMO: CPU interfacingPDF unavailable
70Software CompilationPDF unavailable
71Optimization ExamplesPDF unavailable
72Loop optimizations 1PDF unavailable
73Loop optimizations 2PDF unavailable
74Loop optimizations 3PDF unavailable
75Software pipelining 1PDF unavailable
76Software pipelining 2PDF unavailable
77FFT OptimizationPDF unavailable
78Demo: Vivado setupPDF unavailable
79Background: CPUs and FPGAsPDF unavailable
80Demo: Vivado HLS FFT IP ExportPDF unavailable
81Demo: Vivado ILA and VIO on hardwarePDF unavailable
82Demo: FFT on FPGA boardPDF unavailable
83Demo: Simulating SoC and SDKPDF unavailable
84Background: Understanding ELF filesPDF unavailable
85On-chip communication basicsPDF unavailable
86Many-to-Many communicationPDF unavailable
87AXI bus handshakingPDF unavailable
88AXI bus (contd)PDF unavailable
89Demo: Microblaze processor on FPGAPDF unavailable
90Demo: Performance counter AXI peripheralPDF unavailable
91Demo: HW accelerator for FPGAPDF unavailable
92DMA and arbitrationPDF unavailable
93Network-on-chip basicsPDF unavailable
94NoC - topologies and metricsPDF unavailable
95NoC - routingPDF unavailable
96NoC - switching and flow controlPDF unavailable
97Systolic Arrays - BackgroundPDF unavailable
98Systolic Arrays - ExamplesPDF unavailable
99CORDIC algorithmPDF unavailable
100Parallel implementation of FIR filtersPDF unavailable
101Unfolding TransformationPDF unavailable
102Lookahead TransformationPDF unavailable
103Introduction to GPUs and Matrix multiplicationPDF unavailable

Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available