Lecture 23 : Logical Effort of Multistage Logic Networks
contd...
Example of Minimizing delay: Consider the path from A to B involving three two input NAND gates as
in fig 23.22. The input capacitance of first gate is C and the load capacitance is also C . Find the
least delay in this path and how should the transistors be sized to achieve least delay?
Solution:
Logical effort of a two input NAND gate is g = 4/3
so G = (4/3)*3 = 64/27 = 2.37 .
B = 1 (as there is no branching) ,
H = Cout / Cin = 1
Path Effort F = 64/27*1*1 = 64/27
if each stage has same parasitic delay then P = p1+ p2+p3 =6 pinv ( as all
are two input), then
Fig 23.22: Example Circuit
As,
So, Cz = g3 * C/ (4/3) = C,
Cy = g2 * C/ (4/3) = C.
