Lecture 23 : Logical Effort of Multistage Logic Networks
23.2 Minimizing Delay along a Path
Consider two path stages as in figure 23.21.
The total delay of the above circuit is given by-
substituting in equation for D we get,
To minimise D , we take the partial derivative of D with respect to
Fig 23.21: An Example Circuit
equating it to zero we get,
i.e. the product of logical effort and electrical effort of each stage should be equal to get minimum delay.This is independent of scale of circuit and of the parasitic delay.The delay in the two stages will differ only if the parasitic delays are different.
