Lecture 23 : Logical Effort of Multistage Logic Networks
23.1 Logical Effort of Multistage Logic Networks
The logical effort along a path compounds by multiplying the logical effort of all
the logic gates along the path.We denote it by the letter 'G'. Hence,
The electrical effort along a path through the network is simply the ratio of the capacitance that loads the logic gate in the path to input capacitance of the first gate in the
path.We denote it by the letter 'H' .
When fanout occurs within a logic network, some of the available drive current is directed along the path we are analyzing, and some are directed off that path. Branching effort (b) at the output of a logic gate is defined as-
where is the load capacitance along the path and is the
capacitance of connections that lead off the path.If there is no branching in the path the
branching effort is unity.
Branching effort along the entire path 'B' is the product of branching effort at each of the stages along the path.-
Path effort(F) is defined as-
The path branching and electrical effort are related to the electrical effort of each stage as-
The path delay D is the sum of the delays of each of the stages of logic in the path.
where DF is path effort delay and P is path parasitic delay which are given as -
is the load capacitance along the path and 
is the
capacitance of connections that lead off the path.If there is no branching in the path the
branching effort is unity.
