1. Introduction

In the last two modules, we discussed that in case of digital VLSI design we start with high-level system specifications, which are transformed into optimal Register Transfer Level (RTL) circuits using High Level Synthesis (HLS) algorithms. The optimizations can be in terms of area, speed, power, testability etc., although we have discussed only about area and speed. Once the RTL circuit is available, we need to transform it to gate level design, which can then be processed by backend algorithm; this process is called Logic Synthesis. Formally speaking, Boolean logic synthesis is a process by which an abstract form of desired circuit behavior, typically RTL, is transformed into a design implementation in terms of logic gates and flip-flops [1]. This module is dedicated to logic synthesis of combinational and sequential circuits.

It may be noted that two levels of logic are minimum required to implement an arbitrary Boolean function. Generally, we assume that the primitives are AND and OR gates and Inverters. AND gates are used at the first level and OR gates are used in the second level. Inverters may be present at some inputs of the gates of the first level, but it is not considered as an additional level. Many other choices are also possible namely, using OR gates at first level and AND gates in the second, using NOR and NAND gates etc. It is also possible to implement a circuit in more than two levels, however, it is more complex procedure. In this triple lecture, we will first discuss two level logic synthesis procedures. Latter in this module, we will discuss multilevel synthesis.

There are two main reasons why we may want to implement a circuit in two levels, rather than multiple levels namely, speed of operation and simplicity of the algorithms. However, in practical cases two level implementation may not be possible. Reducing the number of levels increase the fanin and fanout counts of gates. Gates having high fanins and fanouts are slow. Therefore, design libraries do not generally have gates with more than four fanins; this requires multiple level synthesis. Figure 1 illustrates this fact. Say we have a Boolean function asIf we want to have two level implementation, then as shown in Figure 1(a) then we need an AND gate having 6 fanins. If we have gates with 3 maximum fanins, a multilevel implementation is shown in Figure 1 (b).

However, two-level implementation is important to be studied. Two-level implementations are easier to design and analyze because the solution space is greatly restricted. Further, before the development of CMOS logic gates, Boolean functions were realized using Programmable Logic Array (PLAs) and Programmable Array Logic (PALs) [2]. These programmable arrays can implement any combinational logic circuit. Broadly speaking, they have a set of programmable AND planes, which connect to a set of programmable OR planes; this arrangement is two level AND-OR realization that can implement functions in terms of sum of products. In addition, the outputs could be conditionally complemented when required. As PLAs and PALs worked on “product of sum (POS)/sum of product (SOP)” based representation, the algorithms for the optimum implementation of two-level functions were developed in the fifties [3,4].

With the introduction of CMOS based standard cell and semi-custom design methodologies, there was a decline in the popularity of PLAs and PALs [5]. When implementing a circuit with standard cells, it is customary to use multi-level implementation because generally a CMOS gate has a maximum of 4 fanins. The cost in terms of area or speed of a multi-level implementation is not directly related to the cost of an equivalent two-level circuit. However, the role of the two-level techniques is still important, because optimization of multilevel logic involves a network whose nodes represent functions, which are represented as two-level circuits. Therefore, in this (triple) lecture we discuss two-level Boolean logic synthesis (i.e., optimized two level implementation of a circuit for a given Boolean function). Following that, latter in this module we will also discuss multilevel logic synthesis.