4.3 Switching characteristics

In the second chapter, we have already studied the configuration, static characteristics, and noise margins of a CMOS inverter circuit. The switching characteristics of MOS circuits (e.g. the inverter) depend on the charging and discharging of the load capacitance C_L through the PMOS and NMOS transistors respectively. The finite time taken for this charging and discharging is the reason for the delay in circuits. Once we have the estimation of capacitance and resistances associated with a circuit, we can calculate the delays.

Manual analysis of MOS circuits where each capacitor is considered individually is almost impossible because many nonlinear capacitors are associated with a MOS transistor. The capacitance depends on the voltage applied and is distributed among the gate, source, drain, and body regions. To make the analysis possible, once assume that all capacitances are lumped together into one single capacitance C_L , located between V_out and ground. Fig 4.4 shows the schematic of a cascaded inverter pair and with the parasitic capacitances associated. The components of C_L are as follows: