Consider the metal lines shown in Fig 4.3. Three metal 1 wires are running adjacent to each other and going into the page. The metal 2 wire runs on top of these wires. All the dimensions in the vertical direction (i.e. H and T) are established during the fabrication process. The width W, spacing S and length L are the design variables.

When we consider the centre wire on metal 1, it has many sources of capacitance. First, there are two area capacitances between it and the substrate below and the metal 2 above that depend on T1 and T2, respectively. Second, there is lateral capacitance between adjacent wires on the same level that is dependent on the spacing S1. Finally, there are fringing capacitance between the conductor side walls and the upper conductor and lower substrate. The total capacitances on the middle wire would be the sum of all the capacitances. Extracting the value of all these capacitances would require three-dimensional analysis of the structure.

Interwire capacitance becomes a dominant factor in a multilayer interconnects structure and measures are taken to reduce the capacitance. A designer can space out wires by making S large as possible. From a technology perspective, one can increase T1 and T2 and also can introduce materials with low k values as interlayer dielectric to reduce the overall capacitance.