Digital logic circuits exhibit finite rise and fall delays as well as finite propagation times due to capacitances and resistances associated with the gates. The following section discusses simple models to estimate the delays.

4.3.1 Analytic delay models

The CMOS inverter switching characteristics can be studied by the switch model given in Fig 4.5. The transistor can be considered as a switch with an infinite off-resistance for | V_GS | < | V_T | and a finite on-resistance for | V_GS | > | V_T |. When the input makes a step change from low to high, the pull-down transistor is turned on and the pull-up transistor turns off. This situation is shown in Fig 4.5a, and the resulting high resistance of an off PMOS device modeled as a switch open. The NMOS transistor is on and the finite on resistance is modeled as R_n. The time required for V_out to discharge from V_OH to the 50 % point can be calculated by the capacitance discharging through the pull-down device. When the input makes a step change from high to low, the pull-down transistor is turned off and the pull-up transistor turns on. This situation is shown in Fig 4.5b. The off NMOS transistor is shown as a switch open. The PMOS is on and is modeled by as R_p , its on resistance. The time required for V_out to change from V_OL to the 50% point can be calculated by the capacitance charging through the pull-up device.