Limitations

Because ion implantation causes damage to the crystal structure of the target which is often unwanted, ion implantation processing is often followed by a thermal annealing. This can be referred to as damage recovery. As the energetic ions are introduced in the Si lattice, many Si atoms are knocked off their lattice positions resulting in large numbers of Si interstitial atoms and vacant lattice sites (Frenkel pairs). Since the as-implanted dopants are usually electrically non-active and the lattice damage deteriorates the device performance, it is necessary to have the annealing of the implanted sample at temperatures high enough to permit the dopant atoms to incorporate into substitutional sites and thus become electrically active, and for the defects to annihilate and thus repair the damage.

The diffusion of impurities in implanted Si during thermal anneal is complicated as a result of the presence of implantation damage. As an example, the diffusivity of B in implanted crystalline Si is anomalously high compared to equilibrium values. This phenomenon has important consequences for Si processing, since it causes the dopant profile to spread significantly compared to the as-implanted profile during the subsequent annealing steps required for dopant activation. The presence of damage also causes dopant clustering and thus prevents complete electrical activation. The down-scaling of Si CMOS devices requires simultaneously the formation of ultra shallow junctions for the source and drain extensions and a low sheet resistance (high carrier concentration). Conventionally, there is a compromise involved in maximizing dopant electrical activation while minimizing dopant diffusion.