Logic Threshold Voltage Levels

The Fig. 3 provides a comparison between the Input and Output [I / O] logic switching levels for CMOS, and TTL logic families. V_OH and V_OL represent the high and the low logic output levels of a gate respectively. The regions of acceptable high and low voltages are determined by the V_IH and V_IL voltage levels, respectively. Consider the TTL logic, the range for V_IL is from 0 to 0.8 V as shown and the range for V_OL is from 0 to 0.35 V. The region between 0.8 V to 2.0 V is called undefined region. The range for V_IH is from 2.0 V to V _CC and the range of V_OH is from 2.0 V to V_CC. Similarly, for a CMOS the values can be inferred from the diagram.

If one use a CMOS IC for reduced current consumption and a TTL IC feeds the CMOS chip, then you need to either provide a voltage translation or use one of the mixed CMOS/TTL devices. The mixed TTL/CMOS devices are CMOS devices, which just happen to have TTL input trigger levels, but they are CMOS ICs. Let us consider the TTL to CMOS interface briefly. TTL device need a supply voltage of 5 V, while CMOS devices can use any supply voltage from 3 to 10 V. One approach to TTL/CMOS interfacing is to use a 5V supply for both the TTL driver and the CMOS load. In this case, the worst case TTL output voltages are almost compatible with the worst case CMOS input voltages. There is no problem with the TTL low state window (0 to 0.35 V) because it fits inside the CMOS low state window (0 to 1.3 V). This means the CMOS load always interprets the TTL low state drive as low.