Figure 3(a) shows a 2 input CMOS NAND Gate where the TN1 and TP1 have the same input A and TN2 and TP2 has the same input B. When both the A and B are high, TN1 and TN2 are ON and TP1 and TP2 are OFF. Therefore, the output is at logic 0. On the other hand, when both input A and input B are logic 0, TN1 and TN2 is OFF and T P1 and TP2 are ON. Hence, the output is at V CC , logic 1. Similar situation arises when any one of the input is logic 0. In such a case, one of the bottom series transistors i.e. either TN1 or TN2 would be OFF forcing the output to logic 1.
Figure 3(b) shows a 2 input CMOS NOR Gate where the T N1 and T P1 have the same input A and TN2 and TP2 has the same input B. When both the A and B are logic 0, TN1 and TN2 are OFF and TP1 and TP2 are ON. Therefore, the output is at logic 1. On the other hand, when at least one of the inputs A or B is logic 1, the corresponding nMOS transistor would be ON making the output logic 0. The output is disconnected from VCC in such case because at least one of the TP1 or TP2 is OFF. Thus the CMOS circuit of Figure 3(b) acts as a NOR Gate.