CMOS Logic                                                                                                                               Print this page
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The problem is with TTL high state, which can be as low as 2.0 V. The CMOS device needs at least 3.7V for high state input. Typically what is done is to use a pull-up resistor between the TTL driver and the CMOS load. The other end of pull up resistor is connected to VCC. When the TTL output is low, this pull up resistor does not have any effect on this output voltage. Nevertheless, when the TTL output is high, the pull up resistor raises this output to approximately 5 V.

 

 
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