| |
| 32.1 Non-Volatile Read-Write Memory |
| The architecture of Non-Volatile Read-Write (NVRW) Memory is virtually identical to the ROM structure. The memory core consists of an array of transistors placed on the wordline/bitline grid. Selectively disabling or enabling some of the devices programs the memory. In a ROM, this is accomplished by mask-level alterations. In a NVRW memory, a modified transistor that permits its threshold to be altered electrically is used. This modified threshold is retained indefinitely (or atleast for the lifetime, typically of the order of 10 yrs) even when the supply is turned off. To reprogram the memory, the programmed values must be erased, after which a new programming round must be started. The method of erasing is the main differentiating factor between the various classes of reprogrammable nonvolatile memories. The programming of the memory is typically an order of magnitude slower than the reading operation. |
| |
| |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
|
