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| 21.1 Delay in a Logic Gate |
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| Delays in a MOS gate are caused by the capacitive loads and due to the gate
topology. We will take an inverter as the unit gate and compare performance of other
gates with an inverter. A complex logic gate, which may have transistors connected in
series, will have more delay than an inverter with similar transistor sizes that drives the
same load, as they are poorer at driving current. The method of logical effort quantifies
these effects. |
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We will consider  as the delay unit that characterizes a given MOS process. is about
50ps for a typical 0.6 process. |
The absolute delay of the gate is  , Where d is unitless delay of the gate. |
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| The delay incurred by a logic gate can be expressed as, d = f + p , Where
p is a fixed part called parasitic delay and |
f is proportional to the load on the gate’s output called the effort delay or stage
effort. d is measured in units of .
The effort delay f depends on the load and on the properties of the logic gate driving that load and comprises of two components. f = gh ,Where g, logical effort, accounts for the properties of the gate h, electrical effort, characterizes the load. |
| Combining above equations, we get - d = gh + p |
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| Thus, we see that there are four components that basically contribute to delay, namely,,
g, h and p. The process parameter represents the speed of the basic transistor. The
parasitic delay, p, represents the intrinsic delay of the gate due to its own internal
capacitance. The electrical effort, h, is Cout/Cin, where Cout is the capacitance due to the
load and Cin is the capacitance due to sizes of the transistors. The logical effort, g,
expresses the effect of circuit topology and is independent of load and transistor sizing.
Thus logical effort depends only on circuit topology. |
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