| 21.2 Definition of Logical Effort |
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| The method of logical effort is an easy way to estimate the delay in an MOS circuit.
The method can be used to decide the number of logic stages on a path and also what
should be the size of the transistors. Using this method we can do a simple estimations in
the early stages of design, which can be a starting point for more optimizations. |
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| The logical effort of a gate tells how much worse it is at producing output current than an
inverter, given that each of its inputs may contain only the same input capacitance as the
inverter. Reduced output current means slower operation, and thus logical effort number
for a logic gate tells how much more slowly it will drive a load than an inverter would. |
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| Equivalently, logical effort is how much more input capacitance a gate presents to deliver
the same output current as an inverter. |
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As we can see from the table presented above, the logical effort increases as the
complexity of a gate increases. Also, for the same logic gate, as the number of inputs
increases, the logical effort increases. Thus, larger or more complex logic gates will
exhibit more delay. |
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| Thus we can evaluate different choices of logical structure by considering their logical
effort. For example, designs that minimize the number of stages will require more inputs
for each logic gate and thus have larger logical effort. Similarly, designs with fewer
inputs and thus less logical effort per stage may require more stages of logic. These
tradeoffs should be evaluated for an optimum design. |
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