The First Instruction

• Accessing the first instruction
  • Take the starting PC
  • Access iTLB with the VPN extracted from PC: iTLB miss
  • Invoke iTLB miss handler
  • Calculate PTE address
  • If PTEs are cached in L1 data and L2 caches, look them up with PTE address: you will miss there also
  • Access page table in main memory: PTE is invalid: page fault
  • Invoke page fault handler
  • Allocate page frame, read page from disk, update PTE, load PTE in iTLB , restart fetch

• Now you have the physical address
  • Access Icache : miss
  • Send refill request to higher levels: you miss everywhere
  • Send request to memory controller (north bridge)
  • Access main memory
  • Read cache line
  • Refill all levels of cache as the cache line returns to the processor
  • Extract the appropriate instruction from the cache line with the block offset
• This is the longest possible latency in an instruction/data access