TLB Access

• For every cache access (instruction or data) you need to access the TLB first
• Puts the TLB in the critical path
• Want to start indexing into cache and read the tags while TLB lookup takes place
  • Virtually indexed physically tagged cache
  • Extract index from the VA, start reading tag while looking up TLB
  • Once the PA is available do tag comparison
  • Overlaps TLB reading and tag reading

Memory op Latency

• L1 hit: ~1 ns
• L2 hit: ~5 ns
• L3 hit: ~10-15 ns
• Main memory: ~70 ns DRAM access time + bus transfer etc. = ~110-120 ns
• If a load misses in all caches it will eventually come to the head of the ROB and block instruction retirement (in-order retirement is a must)
• Gradually, the pipeline backs up, processor runs out of resources such as ROB entries and physical registers
• Ultimately, the fetcher stalls: severely limits ILP