States of a Cache Line

• The life of a cache line starts off in invalid state (I)
• An access to that line takes a cache miss and fetches the line from main memory
• If it was a read miss the line is filled in shared state (S) [we will discuss it later; for now just assume that this is equivalent to a valid state]
• In case of a store miss the line is filled in modified state (M); instruction cache lines do not normally enter the M state (no store to Icache )
• The eviction of a line in M state must write the line back to the memory (this is called a writeback cache); otherwise the effect of the store would be lost

Inclusion Policy

• A cache hierarchy implements inclusion if the contents of level n cache (exclude the register file) is a subset of the contents of level n+1 cache
  • Eviction of a line from L2 must ask L1 caches (both instruction and data) to invalidate that line if present
  • A store miss fills the L2 cache line in M state, but the store really happens in L1 data cache; so L2 cache does not have the most up-to-date copy of the line
  • Eviction of an L1 line in M state writes back the line to L2
  • Eviction of an L2 line in M state first asks the L1 data cache to send the most up-to-date copy (if any), then it writes the line back to the next higher level (L3 or main memory)
  • Inclusion simplifies the on-chip coherence protocol