Module 9: Addendum to Module 6: Shared Memory Multiprocessors
  Lecture 18: Sharing Patterns and Cache Coherence Protocols
 


State Transition

MESI Example

  • Take the following example
    • P0 reads x, P0 writes x, P1 reads x, P1 writes x, …

P0 generates BusRd , memory provides line, P0 puts line in cache in E state
P0 does write silently, goes to M state
P1 generates BusRd , P0 provides line, P1 puts line in cache in S state, P0 transitions to S state
Rest is identical to MSI

    • Consider this example: P0 reads x, P1 reads x,…

 


P0 generates BusRd , memory provides line, P0 puts line in cache in E state
P1 generates BusRd , memory provides line, P1 puts line in cache in S state, P0 transitions to S state (no cache-to-cache sharing)
Rest is same as MSI