MSI Example

• Take the following example
  • P0 reads x, P1 reads x, P1 writes x, P0 reads x, P2 reads x, P3 writes x
  • Assume the state of the cache line containing the address of x is I in all processors

P0 generates BusRd , memory provides line, P0 puts line in S state
P1 generates BusRd , memory provides line, P1 puts line in S state
P1 generates BusUpgr , P0 snoops and invalidates line, memory does not respond, P1 sets state of line to M
P0 generates BusRd , P1 flushes line and goes to S state, P0 puts line in S state, memory writes back
P2 generates BusRd , memory provides line, P2 puts line in S state
P3 generates BusRdX , P0, P1, P2 snoop and invalidate, memory provides line, P3 puts line in cache in M state

MESI Protocol

• The most popular invalidation-based protocol e.g., appears in Intel Xeon MP
• Why need E state?
  • The MSI protocol requires two transactions to go from I to M even if there is no intervening requests for the line: BusRd followed by BusUpgr
• Save one transaction by having memory controller respond to the first BusRd with E state if there is no other sharer in the system
• Needs a dedicated control wire that gets asserted by a sharer (wired OR)
• Processor can write to a line in E state silently